Cache bandwidth per tick for modern CPUs

Posted by osgx on Stack Overflow See other posts from Stack Overflow or by osgx
Published on 2010-03-01T00:51:01Z Indexed on 2010/04/22 23:03 UTC
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cpu

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cpu-architecture

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cache

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Performance

Hello

What is a speed of cache accessing for modern CPUs? How many bytes can be read or written from memory every processor clock tick by Intel P4, Core2, Corei7, AMD?

Please, answer with both theoretical (width of ld/sd unit with its throughput in uOPs/tick) and practical numbers (even memcpy speed tests, or STREAM benchmark), if any.

PS it is question, related to maximal rate of load/store instructions in assembler. There can be theoretical rate of loading (all Instructions Per Tick are widest loads), but processor can give only part of such, a practical limit of loading.

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