I'm spec-ing the suitability of a dsPIC microcontroller for an analog-to-digital application. This would be preferable to using dedicated A/D chips and a separate dedicated DSP chip.

To do that, I've had to run through some computations, pulling the relevant parameters from the datasheets. I'm not sure I've got it right -- would appreciate a check!

(EDITED NOTE: The PIC10F220 in the example below was selected ONLY to walk through a simple example to check that I'm interpreting Tacq, Fosc, TAD, and divisor correctly in working through this sort of Nyquist analysis. The actual chips I'm considering for the design are the dsPIC33FJ128MC804 (with 16b A/D) or dsPIC30F3014 (with 12b A/D).)

A simple example:

PIC10F220 is the simplest possible PIC with an ADC
Runs at clock speed of 8MHz.
Has an instruction cycle of 0.5us  (4 clock steps per instruction)

So:

Taking Tacq = 6.06 us  (acquisition time for ADC, assume chip temp. = 50*C) 
                       [datasheet p34]

Taking Fosc = 8MHz     (? clock speed)
Taking divisor = 4     (4 clock steps per CPU instruction)
This gives TAD = 0.5us (TAD = 1/(Fosc/divisor) )
Conversion time is 13*TAD  [datasheet p31]
This gives conversion time 6.5us
ADC duration is then 12.56 us   [? Tacq + 13*TAD]

Assuming at least 2 instructions for load/store:

This is another 1 us  [0.5 us per instruction]
Which would give max sampling rate of 73.7 ksps   (1/13.56)

Supposing 8 more instructions for real-time processing:

This is another 4 us
Thus, total ADC/handling time = 17.56us   (12.56us + 1us + 4us)

So expected upper sampling rate is 56.9 ksps.

Nyquist frequency for this sampling rate is therefore 28 kHz.

If this is right, it suggests the (theoretical) performance suitability of this chip's A/D is for signals that are bandlimited to 28 kHz.

Is this a correct interpretation of the information given in the data sheet in obtaining the Nyquist performance limit?

Any opinions on the noise susceptibility of ADCs in PIC / dsPIC chips would be much appreciated!

AKE