Implicit Memory Barriers

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Published on 2010-05-13T05:31:04Z Indexed on 2010/05/13 5:34 UTC
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let's say i have variables A, B and C that two threads (T1, T2) share.
i have the following code:

//T1  
//~~

A = 1;  
B = 1;  
C = 1;

InterlockedExchange(ref Foo, 1);

//T2  (executes AFTER T1 calls InterlockedExchange)  
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

InterlockedExchange(ref Bar, 1);

WriteLine(A);  
WriteLine(B);  
WriteLine(C);  

Question:
does calling InterlockedExchange (implicit full fence) on T1 and T2, gurentess that T2 will "See" the write done by T1 before the fence? (A, B and C variables), even though those variables are not plance on the same cache-line as Foo and Bar?

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