I'm working with an i.mx35 armv6 core processor. I have Interrupt 62 configured as a FIQ with my handler installed and being called. My handler at the moment just toggles an output pin so I can test latency with a scope. With the code below, once I trigger the FIQ it continues forever as fast as it can, apparently not being acknowledged. I'm triggering the FIQ by means of the Interrupt Force Register so I'm assured that the source isn't triggering it this fast. If I disable Interrupt 62 in the AVIC in my FIQ routine the interrupt only triggers once.

I have read the sections on the VIC Port in the ARM1136JF-S and ARM1136J-S Technical Reference Manual and it covers proper exit procedure. I'm only having one FIQ handler so I have no need to branch. The line that I don't understand is:

STR R0, [R8,#AckFinished]

I'm not sure what AckFinished is supposed to be or what this command is supposed to do.

My FIQ handler is below:

ldr r9, IOMUX_ADDR12
ldr r8, [r9]
orr r8, #0x08                        @ top LED
str r8,[r9]                          @turn on LED
bic r8, #0x08                        @ top LED
str r8,[r9]                          @turn off LED

subs pc, r14, #4
IOMUX_ADDR12:   .word 0xFC2A4000 @remapped IOMUX addr

My handler returns just fine and normal system operation resumes if I disable it after the first go, otherwise it triggers constantly and the system appears to hang.

Do you think my assumption is right that the core isn't acknowledging the AVIC or could there be another cause of this FIQ triggering?