When modeling a virtual circuit board, what is the best design pattern to check for cycles?
Posted
by
Wallace Brown
on Programmers
See other posts from Programmers
or by Wallace Brown
Published on 2012-11-02T14:52:19Z
Indexed on
2012/11/02
17:29 UTC
Read the original article
Hit count: 391
To make it simple assume you have only AND and OR gates. Each has two inputs and one output. The output of two inputs can be used as an input for the next gate For example:
A AND B -> E
C AND D -> F
E OR F -> G
Assuming an arbitrary number of gates, we want to check if the circuit ever connects back into itself at an earlier state? For example:
E AND F -> A
This should be illegal since it creates an endless cycle. What design pattern would best be able to check for these cycles?
© Programmers or respective owner
