Hi! I have a directory in which I keep adding different C++ source files, and generic Makefile to compile them. This is the content of the Makefile: .PHONY: all clean CXXFLAGS = -pipe -Wall -Wextra -Weffc++ -pedantic -ggdb SRCS = $(wildcard *.cxx) OBJS = $(patsubst %.cxx,%.out,$(SRCS)) all: $(OBJS) clean: rm -fv $(OBJS) %.out: %.cxx $(CXX) $(CXXFLAGS) $^ -o $@ NOTE: As is obvious from above, I am using *.out for executable file extensions (and not for object file). Also, there are some files which are compiled together: g++ file_main.cxx file.cxx -o file_main.out To compile such files, until now I have been adding explicit rules in the Makefile: file_main.out: file_main.cxx file.cxx file.out: file_main.out @echo "Skipping $@" But now my Makefile has a lot of explicit rules, and I would like to replace them with a simpler implicit rule. Any idea how to do it?