makefile pattern rules: single wildcard, multiple instances in prerequisite
- by johndashen
Hi all, hopefully this is a basic question about make pattern rules:
I want to use a wildcard more than once in a prerequisite for a rule, i.e. in my Makefile I have
data/%P1.m: $(PROJHOME)/data/%/ISCAN/%P1.RAW
@echo " Writing temporary matlab file for $*"
# do something
data/%P2.m: $(PROJHOME)/data/%/ISCAN/AGP2.RAW
@echo " Writing temporary matlab file for $*"
# do something
In this example, I try to invoke make when the wildcard % is AG. Both files $(PROJHOME)/data/AG/ISCAN/AGP1.RAW and $(PROJHOME)/data/AG/ISCAN/AGP2.RAW exist. I attempt the following make commands and get this output:
[jshen@iLab10 gender-diffs]$ make data/AGP1.m
make: *** No rule to make target `data/AGP1.m'. Stop.
[jshen@iLab10 gender-diffs]$ make data/AGP2.m
Writing temporary matlab file for AG, part 2...
[jshen@iLab10 gender-diffs]$ ls data/AG/ISCAN/AG*
data/AG/ISCAN/AGP1.RAW data/AG/ISCAN/AGP2.RAW
How can I implement multiple instances of the same wildcard in the first make rule?
