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  • Can an SSD notify the hosting OS that its wear level is getting high?

    - by Tony_Henrich
    I read a lot about SSDs and I am interested in them for server use. My biggest concern is their reliability. A lot of writes shortens their life span. I can mitigate this problem if I can run some kind of diagnostics on a regular basis on the SSD or if the SSD can automatically warn the OS that its reliability is reaching a critical level. Think of this as S.M.A.R.T or software like SpinRite for SSDs. Does anything I mentioned exist now? Which kind/brand of SSD does this? I don't mind swapping out a tired SSD for a newer one once a while. I am pretty sure that SSDs life is calculated in years and not in few months? For me, the improved performance will pay for the SSD over and over. I am planning to use plenty of RAM as well.

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  • Best way to run multiple queries per second on database, performance wise?

    - by Michael Joell
    I am currently using Java to insert and update data multiple times per second. Never having used databases with Java, I am not sure what is required, and how to get the best performance. I currently have a method for each type of query I need to do (for example, update a row in a database). I also have a method to create the database connection. Below is my simplified code. public static void addOneForUserInChannel(String channel, String username) throws SQLException { Connection dbConnection = null; PreparedStatement ps = null; String updateSQL = "UPDATE " + channel + "_count SET messages = messages + 1 WHERE username = ?"; try { dbConnection = getDBConnection(); ps = dbConnection.prepareStatement(updateSQL); ps.setString(1, username); ps.executeUpdate(); } catch(SQLException e) { System.out.println(e.getMessage()); } finally { if(ps != null) { ps.close(); } if(dbConnection != null) { dbConnection.close(); } } } And my DB connection private static Connection getDBConnection() { Connection dbConnection = null; try { Class.forName(DB_DRIVER); } catch (ClassNotFoundException e) { System.out.println(e.getMessage()); } try { dbConnection = DriverManager.getConnection(DB_CONNECTION, DB_USER,DB_PASSWORD); return dbConnection; } catch (SQLException e) { System.out.println(e.getMessage()); } return dbConnection; } This seems to be working fine for now, with about 1-2 queries per second, but I am worried that once I expand and it is running many more, I might have some issues. My questions: Is there a way to have a persistent database connection throughout the entire run time of the process? If so, should I do this? Are there any other optimizations that I should do to help with performance? Thanks

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  • When machine code is generated from a program how does it translates to hardware level operations ??

    - by user553492
    Like if say the instruction is something like 100010101 1010101 01010101 011101010101. Now how is this translating to an actual job of deleting something from memory? Memory consists of actual physical transistors the HOLD data. What causes them to lose that data is some external signal? I want to know how that signal is generated. Like how some binary numbers change the state of a physical transistor. Is there a level beyond machine code that isn't explicitly visible to a programmer? I have heard of microcode that handle code at hardware level, even below assembly language. But still I pretty much don't understand. Thanks!

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  • How to write php code to input jsonstring and insert to sql server

    - by Romi
    i am trying to OUTPUT a Json String from the phone and to get it uploaded to the sql server i have. I Do not know how to get the output Json and write the php code... i tried many methods but couldnt find a solution. public void post(String string) { HttpClient httpclient = new DefaultHttpClient(); HttpPost httppost = new HttpPost( "http://www.hopscriber.com/xoxoxox/testphp.php"); try { List<NameValuePair> nameValuePairs = new ArrayList<NameValuePair>(); nameValuePairs.add(new BasicNameValuePair("myJson", string)); httppost.setEntity(new UrlEncodedFormEntity(nameValuePairs)); HttpResponse response = httpclient.execute(httppost); String str = inputStreamToString(response.getEntity().getContent()) .toString(); Log.w("SENCIDE", str); } catch (Exception e) { Toast.makeText(getBaseContext(), "notwork", Toast.LENGTH_LONG) .show(); } } private Object inputStreamToString(InputStream is) { // TODO Auto-generated method stub String line = ""; StringBuilder total = new StringBuilder(); // Wrap a BufferedReader around the InputStream BufferedReader rd = new BufferedReader(new InputStreamReader(is)); // Read response until the end try { while ((line = rd.readLine()) != null) { total.append(line); } } catch (IOException e) { e.printStackTrace(); } // Return full string return total; } it outputs a json string as [myJson=[{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"org.siislab.tutorial.permission.READ_FRIENDS","level":"Normal"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"org.siislab.tutorial.permission.WRITE_FRIENDS","level":"Normal"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"org.siislab.tutorial.permission.FRIEND_SERVICE","level":"Normal"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"org.siislab.tutorial.permission.FRIEND_NEAR","level":"Dangerous"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"org.siislab.tutorial.permission.BROADCAST_FRIEND_NEAR","level":"Normal"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"android.permission.RECEIVE_BOOT_COMPLETED","level":"Normal"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"android.permission.READ_CONTACTS","level":"Dangerous"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"android.permission.ACCESS_FINE_LOCATION","level":"Dangerous"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"android.permission.WRITE_EXTERNAL_STORAGE","level":"Dangerous"},{"name":"FriendTracker","user":"amjgp000000000000000","pack":"org.siislab.tutorial.friendtracker","perm":"android.permission.READ_PHONE_STATE","level":"Dangerous"},{"name":"Tesing","user":"amjgp000000000000000","pack":"com.example.tesing","perm":"null","level":"null"},{"name":"Action Bar","user":"amjgp000000000000000","pack":"name.brucephillips.actionbarexample","perm":"null","level":"null"},.......

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  • How can I bind the second argument in a function but not the first (in an elegant way)?

    - by Frank Osterfeld
    Is there a way in Haskell to bind the second argument but not the first of a function without using lambda functions or defining another "local" function? Example. I have a binary function like: sub :: Int -> Int -> Int sub x y = x - y Now if I want to bind the first argument, I can do so easily using (sub someExpression): mapSubFrom5 x = map (sub 5) x *Main> mapSubFrom5 [1,2,3,4,5] [4,3,2,1,0] That works fine if I want to bind the first n arguments without "gap". If I want to bind the second argument but not the first, the two options I am aware of are more verbose: Either via another, local, function: mapSub5 x = map sub5 x where sub5 x = sub x 5 *Main> mapSub5 [1,2,3,4,5] [-4,-3,-2,-1,0] Or using lambda: mapSub5 x = map (\x -> sub x 5) x While both are working fine, I like the elegance of "sub 5" and wonder if there is a similarly elegant way to bind the n-th (n 1) argument of a function?

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  • NEC uPD720200 USB 3.0 not working on Ubuntu 12.04

    - by Jagged
    I've recently installed Ubuntu 12.04 64-bit on a HP Envy 15 1104tx. Most stuff appears to be working fine with the exception of the two USB3 ports (USB2 port works fine). I've read a lot of articles but so far have not been able to find a solution. I've tried adding 'pci=nomsi' to '/etc/default/grub' but this made no difference. Some articles suggest booting into Windows and upgrading the firmware on the uPD720200. Any body had any experience of this? Is there a way I can checked the firmware version of the NEC uPD720200 in Linux to see if there is an update available? Any help appreciated. uname -a: Linux HP-ENVY-15-1104tx 3.2.0-26-generic #41-Ubuntu SMP Thu Jun 14 17:49:24 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux lshw: hp-envy-15-1104tx description: Notebook product: HP ENVY 15 Notebook PC (WF591PA#ABG) vendor: Hewlett-Packard version: 0492110000241910001420000 serial: CNF0301C79 width: 64 bits capabilities: smbios-2.6 dmi-2.6 vsyscall32 configuration: boot=normal chassis=notebook family=103C_5335KV sku=WF591PA#ABG uuid=434E4630-3330-3143-3739-60EB6906688F *-core description: Motherboard product: 1522 vendor: Hewlett-Packard physical id: 0 version: 36.35 serial: CNF0301C79 slot: Base Board Chassis Location *-firmware description: BIOS vendor: Hewlett-Packard physical id: 0 version: F.2B date: 10/12/2010 size: 1MiB capacity: 1472KiB capabilities: pci upgrade shadowing cdboot bootselect edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb biosbootspecification *-memory description: System Memory physical id: 13 slot: System board or motherboard size: 16GiB *-bank:0 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 0 serial: E13C4316 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 1 serial: E03C3E16 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:2 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 2 serial: 672279CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:3 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 3 serial: 652286CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-cpu description: CPU product: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz vendor: Intel Corp. physical id: 1d bus info: cpu@0 version: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz slot: CPU size: 1199MHz capacity: 1199MHz width: 64 bits clock: 1066MHz capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 popcnt lahf_lm ida tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: cores=4 enabledcores=4 threads=8 *-cache:0 description: L3 cache physical id: 1e slot: L3 Cache size: 8MiB capacity: 8MiB capabilities: synchronous internal write-through unified *-cache:1 description: L2 cache physical id: 20 slot: L2 Cache size: 256KiB capacity: 256KiB capabilities: synchronous internal write-through unified *-cache:2 description: L1 cache physical id: 21 slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through instruction *-cache description: L1 cache physical id: 1f slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through data *-pci:0 description: Host bridge product: Core Processor DMI vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 11 width: 32 bits clock: 33MHz *-pci:0 description: PCI bridge product: Core Processor PCI Express Root Port 1 vendor: Intel Corporation physical id: 3 bus info: pci@0000:00:03.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:4000(size=4096) memory:d4100000-d41fffff ioport:c0000000(size=268435456) *-display description: VGA compatible controller product: Broadway PRO [Mobility Radeon HD 5800 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0 bus info: pci@0000:01:00.0 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi vga_controller bus_master cap_list rom configuration: driver=fglrx_pci latency=0 resources: irq:58 memory:c0000000-cfffffff memory:d4100000-d411ffff ioport:4000(size=256) memory:d4140000-d415ffff *-multimedia description: Audio device product: Juniper HDMI Audio [Radeon HD 5700 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0.1 bus info: pci@0000:01:00.1 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:56 memory:d4120000-d4123fff *-pci:1 description: PCI bridge product: Core Processor PCI Express Root Port 3 vendor: Intel Corporation physical id: 5 bus info: pci@0000:00:05.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 memory:d4000000-d40fffff *-usb description: USB controller product: uPD720200 USB 3.0 Host Controller vendor: NEC Corporation physical id: 0 bus info: pci@0000:02:00.0 version: 03 width: 64 bits clock: 33MHz capabilities: pm msi msix pciexpress xhci bus_master cap_list configuration: driver=xhci_hcd latency=0 resources: irq:16 memory:d4000000-d4001fff *-generic:0 UNCLAIMED description: System peripheral product: Core Processor System Management Registers vendor: Intel Corporation physical id: 8 bus info: pci@0000:00:08.0 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:1 UNCLAIMED description: System peripheral product: Core Processor Semaphore and Scratchpad Registers vendor: Intel Corporation physical id: 8.1 bus info: pci@0000:00:08.1 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:2 UNCLAIMED description: System peripheral product: Core Processor System Control and Status Registers vendor: Intel Corporation physical id: 8.2 bus info: pci@0000:00:08.2 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:3 UNCLAIMED description: System peripheral product: Core Processor Miscellaneous Registers vendor: Intel Corporation physical id: 8.3 bus info: pci@0000:00:08.3 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:4 UNCLAIMED description: System peripheral product: Core Processor QPI Link vendor: Intel Corporation physical id: 10 bus info: pci@0000:00:10.0 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:5 UNCLAIMED description: System peripheral product: Core Processor QPI Routing and Protocol Registers vendor: Intel Corporation physical id: 10.1 bus info: pci@0000:00:10.1 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-multimedia description: Audio device product: 5 Series/3400 Series Chipset High Definition Audio vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 05 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:55 memory:d4200000-d4203fff *-pci:2 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:17 ioport:3000(size=4096) memory:d3000000-d3ffffff ioport:d0000000(size=16777216) *-network description: Wireless interface product: Centrino Advanced-N 6200 vendor: Intel Corporation physical id: 0 bus info: pci@0000:03:00.0 logical name: wlan0 version: 35 serial: 00:27:10:40:e4:68 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=iwlwifi driverversion=3.2.0-26-generic firmware=9.221.4.1 build 25532 latency=0 link=no multicast=yes wireless=IEEE 802.11abgn resources: irq:54 memory:d3000000-d3001fff *-pci:3 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:2000(size=4096) memory:d2000000-d2ffffff ioport:d1000000(size=16777216) *-network description: Ethernet interface product: AR8131 Gigabit Ethernet vendor: Atheros Communications Inc. physical id: 0 bus info: pci@0000:04:00.0 logical name: eth0 version: c0 serial: 60:eb:69:06:68:8f size: 1Gbit/s capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vpd bus_master cap_list ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=atl1c driverversion=1.0.1.0-NAPI duplex=full firmware=N/A ip=10.161.0.147 latency=0 link=yes multicast=yes port=twisted pair speed=1Gbit/s resources: irq:57 memory:d2000000-d203ffff ioport:2000(size=128) *-usb description: USB controller product: 5 Series/3400 Series Chipset USB2 Enhanced Host Controller vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 05 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:20 memory:d4205800-d4205bff *-pci:4 description: PCI bridge product: 82801 Mobile PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci@0000:00:1e.0 version: a5 width: 32 bits clock: 33MHz capabilities: pci subtractive_decode bus_master cap_list *-isa description: ISA bridge product: Mobile 5 Series Chipset LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 05 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: RAID bus controller product: 82801 Mobile SATA Controller [RAID mode] vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 version: 05 width: 32 bits clock: 66MHz capabilities: storage msi pm bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:45 ioport:5048(size=8) ioport:5054(size=4) ioport:5040(size=8) ioport:5050(size=4) ioport:5020(size=32) memory:d4205000-d42057ff *-disk description: ATA Disk product: OCZ-VERTEX3 physical id: 0.0.0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 2.15 serial: OCZ-0350P6H316X5KUQE size: 223GiB (240GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=000592dd *-volume:0 description: EXT4 volume vendor: Linux physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 logical name: / version: 1.0 serial: e741f18c-cfc5-4bce-b1e7-f80e517a3a22 size: 207GiB capacity: 207GiB capabilities: primary bootable journaled extended_attributes large_files huge_files dir_nlink recover extents ext4 ext2 initialized configuration: created=2012-06-15 06:49:27 filesystem=ext4 lastmountpoint=/ modified=2012-06-14 21:23:42 mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,user_xattr,barrier=1,data=ordered mounted=2012-07-10 16:18:20 state=mounted *-volume:1 description: Extended partition physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 size: 15GiB capacity: 15GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 15GiB capabilities: nofs *-serial UNCLAIMED description: SMBus product: 5 Series/3400 Series Chipset SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 05 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:d4205c00-d4205cff ioport:5000(size=32) *-pci:1 description: Host bridge product: Core Processor QuickPath Architecture Generic Non-Core Registers vendor: Intel Corporation physical id: 101 bus info: pci@0000:ff:00.0 version: 04 width: 32 bits clock: 33MHz *-pci:2 description: Host bridge product: Core Processor QuickPath Architecture System Address Decoder vendor: Intel Corporation physical id: 102 bus info: pci@0000:ff:00.1 version: 04 width: 32 bits clock: 33MHz *-pci:3 description: Host bridge product: Core Processor QPI Link 0 vendor: Intel Corporation physical id: 103 bus info: pci@0000:ff:02.0 version: 04 width: 32 bits clock: 33MHz *-pci:4 description: Host bridge product: Core Processor QPI Physical 0 vendor: Intel Corporation physical id: 104 bus info: pci@0000:ff:02.1 version: 04 width: 32 bits clock: 33MHz *-pci:5 description: Host bridge product: Core Processor Integrated Memory Controller vendor: Intel Corporation physical id: 105 bus info: pci@0000:ff:03.0 version: 04 width: 32 bits clock: 33MHz *-pci:6 description: Host bridge product: Core Processor Integrated Memory Controller Target Address Decoder vendor: Intel Corporation physical id: 106 bus info: pci@0000:ff:03.1 version: 04 width: 32 bits clock: 33MHz *-pci:7 description: Host bridge product: Core Processor Integrated Memory Controller Test Registers vendor: Intel Corporation physical id: 107 bus info: pci@0000:ff:03.4 version: 04 width: 32 bits clock: 33MHz *-pci:8 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Control Registers vendor: Intel Corporation physical id: 108 bus info: pci@0000:ff:04.0 version: 04 width: 32 bits clock: 33MHz *-pci:9 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Address Registers vendor: Intel Corporation physical id: 109 bus info: pci@0000:ff:04.1 version: 04 width: 32 bits clock: 33MHz *-pci:10 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Rank Registers vendor: Intel Corporation physical id: 10a bus info: pci@0000:ff:04.2 version: 04 width: 32 bits clock: 33MHz *-pci:11 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Thermal Control Registers vendor: Intel Corporation physical id: 10b bus info: pci@0000:ff:04.3 version: 04 width: 32 bits clock: 33MHz *-pci:12 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Control Registers vendor: Intel Corporation physical id: 10c bus info: pci@0000:ff:05.0 version: 04 width: 32 bits clock: 33MHz *-pci:13 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Address Registers vendor: Intel Corporation physical id: 10d bus info: pci@0000:ff:05.1 version: 04 width: 32 bits clock: 33MHz *-pci:14 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Rank Registers vendor: Intel Corporation physical id: 10e bus info: pci@0000:ff:05.2 version: 04 width: 32 bits clock: 33MHz *-pci:15 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Thermal Control Registers vendor: Intel Corporation physical id: 10f bus info: pci@0000:ff:05.3 version: 04 width: 32 bits clock: 33MHz *-battery description: Lithium Ion Battery product: NK06053 vendor: SMP-ATL24 physical id: 1 slot: Primary capacity: 4800mWh configuration: voltage=11.1V lspci: 02:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) (prog-if 30 [XHCI]) Subsystem: Hewlett-Packard Company Device 1522 Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at d4000000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150] Latency Tolerance Reporting Kernel driver in use: xhci_hcd lsusb (with thumb drive plugged into USB3 port): Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 003 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 001 Device 002: ID 8087:0020 Intel Corp. Integrated Rate Matching Hub Bus 001 Device 003: ID 5986:01d0 Acer, Inc Bus 001 Device 004: ID 03f0:231d Hewlett-Packard

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  • Drivers for NVIDIA 520M not working in Ubuntu 12.04

    - by Don
    I am aware that this is nominally a duplicate question, however I've read the other questions and haven't been able to resolve my problem after many hours and attempts, so please don't delete it. Additionally, it seems like many answers to the other questions are specifically dependent on certain situations. My situation being different from the others I found represented, here's my question. Until last night, I had Ubuntu 12.04 installed with Wubi, and it ran ok, though slowly and with occasional hangs. So I partitioned the drive and installed 12.04 in its own partition. Now when I start it, I am stuck using 2D. I believe this is an NVIDIA bug. My NVIDIA card is a GT 520M and my machine has Optimus. Additional Drivers only displays my wireless driver. Going to System Settings Details Graphics shows Driver:Unknown, Experience:Standard. I downloaded the driver from the NVIDIA website, and ran the installer with no errors, except that the "distribution-provided pre-install script failed". After rebooting, my screen was stuck at 640X480, which was fixed by editing /etc/X11/xorg.conf However, I still was stuck in 2D, and nothing else had changed either. A thread suggested something called Bumblebee. I tried that, and when I ran optirun firefoxI got a frozen blank screen. Following another suggestion, I checked the BIOS to try and disable Optimus. I found and ran myriad other commands to try and fix the problem and nothing changed. Now I have just done a clean re-install of Ubuntu. From there, I: Installed all the updates Downloaded the NVIDIA driver Installed it Got screen stuck at 640X480, fixed in xorg.conf. To recap the problem: I can't get the NVIDIA drivers working I am stuck using 2D I'm an idiot I think if the first one is solved, the solution to the second will naturally follow. If you need me to provide any other information, I'd be happy to. From what I've seen in other threads, I think this information may help: lsmod: dh@donsMachine:~$ lsmod Module Size Used by nvidia 12353161 0 snd_hda_codec_hdmi 32474 1 snd_hda_codec_realtek 223867 1 joydev 17693 0 parport_pc 32866 0 ppdev 17113 0 rfcomm 47604 0 bnep 18281 2 bluetooth 180104 10 rfcomm,bnep snd_hda_intel 33773 3 snd_hda_codec 127706 3 snd_hda_codec_hdmi,snd_hda_codec_realtek,snd_hda_intel snd_hwdep 13668 1 snd_hda_codec snd_pcm 97188 3 snd_hda_codec_hdmi,snd_hda_intel,snd_hda_codec uvcvideo 72627 0 videodev 98259 1 uvcvideo v4l2_compat_ioctl32 17128 1 videodev snd_seq_midi 13324 0 snd_rawmidi 30748 1 snd_seq_midi snd_seq_midi_event 14899 1 snd_seq_midi snd_seq 61896 2 snd_seq_midi,snd_seq_midi_event lib80211_crypt_tkip 17390 0 wl 2568210 0 lib80211 14381 2 lib80211_crypt_tkip,wl snd_timer 29990 2 snd_pcm,snd_seq snd_seq_device 14540 3 snd_seq_midi,snd_rawmidi,snd_seq snd 78855 16 snd_hda_codec_hdmi,snd_hda_codec_realtek,snd_hda_intel,snd_hda_codec,snd_hwdep,snd_pcm,snd_rawmidi,snd_seq,snd_timer,snd_seq_device psmouse 87692 0 serio_raw 13211 0 i915 468745 2 soundcore 15091 1 snd snd_page_alloc 18529 2 snd_hda_intel,snd_pcm drm_kms_helper 46978 1 i915 drm 242038 3 i915,drm_kms_helper mei 41616 0 i2c_algo_bit 13423 1 i915 mxm_wmi 12979 0 acer_wmi 28418 0 sparse_keymap 13890 1 acer_wmi video 19596 1 i915 wmi 19256 2 mxm_wmi,acer_wmi mac_hid 13253 0 lp 17799 0 parport 46562 3 parport_pc,ppdev,lp tg3 152032 0 sdhci_pci 18826 0 sdhci 33205 1 sdhci_pci lspci -nn | grep VGA dh@donsMachine:~$ lspci -nn | grep VGA 00:02.0 VGA compatible controller [0300]: Intel Corporation 2nd Generation Core Processor Family Integrated Graphics Controller [8086:0116] (rev 09) 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation Device [10de:0df7] (rev a1) lshw dh@donsMachine:~$ sudo lshw [sudo] password for dh: donsmachine description: Notebook product: EasyNote TS44HR () vendor: Packard Bell version: V1.12 serial: LXBWZ02017134209D71601 width: 64 bits capabilities: smbios-2.7 dmi-2.7 vsyscall32 configuration: boot=normal chassis=notebook uuid=16FE576B-CA15-11E0-B096-B870F4E51243 *-core description: Motherboard product: SJV50_HR vendor: Packard Bell physical id: 0 version: Base Board Version serial: Base Board Serial Number slot: Base Board Chassis Location *-firmware description: BIOS vendor: Packard Bell physical id: 0 version: V1.12 date: 07/11/2011 size: 1MiB capacity: 2496KiB capabilities: pci upgrade shadowing cdboot bootselect edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb biosbootspecification *-memory description: System Memory physical id: 1b slot: System board or motherboard size: 4GiB *-bank:0 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: NT2GC64B88B0NS-CG vendor: Nanya Technology physical id: 0 serial: 598E126E slot: ChannelA-DIMM0 size: 2GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: DIMM [empty] physical id: 1 slot: ChannelA-DIMM1 *-bank:2 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: NT2GC64B88B0NS-CG vendor: Nanya Technology physical id: 2 serial: 159E126C slot: ChannelB-DIMM0 size: 2GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:3 description: DIMM [empty] physical id: 3 slot: ChannelB-DIMM1 *-cpu description: CPU product: Intel(R) Core(TM) i3-2330M CPU @ 2.20GHz vendor: Intel Corp. physical id: 2e bus info: cpu@0 version: Intel(R) Core(TM) i3-2330M CPU @ 2.20GHz slot: CPU1 size: 2GHz capacity: 4GHz width: 64 bits clock: 1333MHz capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer xsave avx lahf_lm arat epb xsaveopt pln pts tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: cores=2 enabledcores=2 threads=4 *-cache:0 description: L1 cache physical id: 30 slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through instruction *-cache:1 description: L2 cache physical id: 31 slot: L2 Cache size: 256KiB capacity: 256KiB capabilities: synchronous internal write-through unified *-cache:2 description: L3 cache physical id: 32 slot: L3 Cache size: 3MiB capacity: 3MiB capabilities: synchronous internal write-through unified *-cache description: L1 cache physical id: 2f slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through data *-pci description: Host bridge product: 2nd Generation Core Processor Family DRAM Controller vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 09 width: 32 bits clock: 33MHz configuration: driver=agpgart-intel resources: irq:0 *-pci:0 description: PCI bridge product: Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port vendor: Intel Corporation physical id: 1 bus info: pci@0000:00:01.0 version: 09 width: 32 bits clock: 33MHz capabilities: pci pm msi pciexpress normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:40 ioport:2000(size=4096) memory:d0000000-d10fffff ioport:a0000000(size=301989888) *-display description: VGA compatible controller product: NVIDIA Corporation vendor: NVIDIA Corporation physical id: 0 bus info: pci@0000:01:00.0 version: a1 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vga_controller bus_master cap_list rom configuration: driver=nvidia latency=0 resources: irq:16 memory:d0000000-d0ffffff memory:a0000000-afffffff memory:b0000000-b1ffffff ioport:2000(size=128) memory:d1000000-d107ffff *-display description: VGA compatible controller product: 2nd Generation Core Processor Family Integrated Graphics Controller vendor: Intel Corporation physical id: 2 bus info: pci@0000:00:02.0 version: 09 width: 64 bits clock: 33MHz capabilities: msi pm vga_controller bus_master cap_list rom configuration: driver=i915 latency=0 resources: irq:43 memory:d1400000-d17fffff memory:c0000000-cfffffff ioport:3000(size=64) *-communication description: Communication controller product: 6 Series/C200 Series Chipset Family MEI Controller #1 vendor: Intel Corporation physical id: 16 bus info: pci@0000:00:16.0 version: 04 width: 64 bits clock: 33MHz capabilities: pm msi bus_master cap_list configuration: driver=mei latency=0 resources: irq:42 memory:d1a04000-d1a0400f *-usb:0 description: USB controller product: 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #2 vendor: Intel Corporation physical id: 1a bus info: pci@0000:00:1a.0 version: 04 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:16 memory:d1a0a000-d1a0a3ff *-multimedia description: Audio device product: 6 Series/C200 Series Chipset Family High Definition Audio Controller vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 04 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:44 memory:d1a00000-d1a03fff *-pci:1 description: PCI bridge product: 6 Series/C200 Series Chipset Family PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: b4 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:17 memory:9fb00000-9fbfffff ioport:d1800000(size=1048576) *-network description: Ethernet interface product: NetLink BCM57785 Gigabit Ethernet PCIe vendor: Broadcom Corporation physical id: 0 bus info: pci@0000:02:00.0 logical name: eth0 version: 10 serial: b8:70:f4:e5:12:43 capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi msix pciexpress bus_master cap_list rom ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=tg3 driverversion=3.121 firmware=sb latency=0 link=no multicast=yes port=twisted pair resources: irq:16 memory:d1830000-d183ffff memory:d1840000-d184ffff memory:d1850000-d18507ff *-generic:0 description: SD Host controller product: NetXtreme BCM57765 Memory Card Reader vendor: Broadcom Corporation physical id: 0.1 bus info: pci@0000:02:00.1 version: 10 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=sdhci-pci latency=0 resources: irq:17 memory:d1800000-d180ffff *-generic:1 UNCLAIMED description: System peripheral product: Broadcom Corporation vendor: Broadcom Corporation physical id: 0.2 bus info: pci@0000:02:00.2 version: 10 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: latency=0 resources: memory:d1810000-d181ffff *-generic:2 UNCLAIMED description: System peripheral product: Broadcom Corporation vendor: Broadcom Corporation physical id: 0.3 bus info: pci@0000:02:00.3 version: 10 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: latency=0 resources: memory:d1820000-d182ffff *-pci:2 description: PCI bridge product: 6 Series/C200 Series Chipset Family PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: b4 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 memory:d1900000-d19fffff *-network description: Wireless interface product: BCM43225 802.11b/g/n vendor: Broadcom Corporation physical id: 0 bus info: pci@0000:03:00.0 logical name: eth1 version: 01 serial: 68:a3:c4:44:81:96 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=wl0 driverversion=5.100.82.38 ip=192.168.0.12 latency=0 multicast=yes wireless=IEEE 802.11bgn resources: irq:17 memory:d1900000-d1903fff *-usb:1 description: USB controller product: 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 04 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:23 memory:d1a09000-d1a093ff *-isa description: ISA bridge product: HM65 Express Chipset Family LPC Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 04 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: SATA controller product: 6 Series/C200 Series Chipset Family 6 port SATA AHCI Controller vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 logical name: scsi1 version: 04 width: 32 bits clock: 66MHz capabilities: storage msi pm ahci_1.0 bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:41 ioport:3098(size=8) ioport:30bc(size=4) ioport:3090(size=8) ioport:30b8(size=4) ioport:3060(size=32) memory:d1a08000-d1a087ff *-disk description: ATA Disk product: ST9500325AS vendor: Seagate physical id: 0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 0001 serial: S2W1AMSX size: 465GiB (500GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=a45f21e9 *-volume:0 description: Windows NTFS volume physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 version: 3.1 serial: 46aa-2a25 size: 19GiB capacity: 20GiB capabilities: primary ntfs initialized configuration: clustersize=4096 created=2011-08-25 21:32:00 filesystem=ntfs label=PQSERVICE state=clean *-volume:1 description: Windows NTFS volume physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 version: 3.1 serial: 10aa-ad1a size: 98MiB capacity: 100MiB capabilities: primary bootable ntfs initialized configuration: clustersize=4096 created=2011-08-25 21:32:03 filesystem=ntfs label=SYSTEM RESERVED state=clean *-volume:2 description: Windows NTFS volume physical id: 3 bus info: scsi@0:0.0.0,3 logical name: /dev/sda3 version: 3.1 serial: 668c5afc-182e-ff4b-b084-3cc09f54972d size: 395GiB capacity: 395GiB capabilities: primary ntfs initialized configuration: clustersize=4096 created=2011-08-25 21:32:03 filesystem=ntfs label=Don's Machine state=clean *-volume:3 description: Extended partition physical id: 4 bus info: scsi@0:0.0.0,4 logical name: /dev/sda4 size: 49GiB capacity: 49GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume:0 description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 3945MiB capabilities: nofs *-logicalvolume:1 description: Linux filesystem partition physical id: 6 logical name: /dev/sda6 logical name: / capacity: 46GiB configuration: mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,user_xattr,barrier=1,data=ordered state=mounted *-cdrom description: DVD-RAM writer product: DVD-RW DVRTD11RS vendor: PIONEER physical id: 1 bus info: scsi@1:0.0.0 logical name: /dev/cdrom logical name: /dev/cdrw logical name: /dev/dvd logical name: /dev/dvdrw logical name: /dev/sr0 version: 1.01 capabilities: removable audio cd-r cd-rw dvd dvd-r dvd-ram configuration: ansiversion=5 status=nodisc *-serial UNCLAIMED description: SMBus product: 6 Series/C200 Series Chipset Family SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 04 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:d1a06000-d1a060ff ioport:3040(size=32) *-power UNCLAIMED description: OEM_Define1 product: OEM_Define5 vendor: OEM_Define2 physical id: 1 version: OEM_Define6 serial: OEM_Define3 capacity: 75mWh *-battery description: Lithium Ion Battery product: CRB Battery 0 vendor: -Virtual Battery 0- physical id: 2 version: 10/12/2007 serial: Battery 0 slot: Fake

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  • Error when I try to installth desktop integration features for Openoffice

    - by PENG TENG
    peng@peng-ThinkPad-SL410:~$ cd '/home/peng/Downloads/en-US/DEBS/desktop-integration' peng@peng-ThinkPad-SL410:~/Downloads/en-US/DEBS/desktop-integration$ sudo dpkg -i *.deb (Reading database ... 357248 files and directories currently installed.) Unpacking openoffice.org-debian-menus (from openoffice.org3.4-debian-menus_3.4-9593_all.deb) ... dpkg: error processing openoffice.org3.4-debian-menus_3.4-9593_all.deb (--install): trying to overwrite '/usr/bin/soffice', which is also in package libreoffice-common 1:3.6.2~rc2-0ubuntu3 /usr/bin/gtk-update-icon-cache gtk-update-icon-cache: Cache file created successfully. /usr/bin/gtk-update-icon-cache gtk-update-icon-cache: Cache file created successfully. Processing triggers for menu ... Processing triggers for hicolor-icon-theme ... Processing triggers for gnome-icon-theme ... Processing triggers for shared-mime-info ... Unknown media type in type 'all/all' Unknown media type in type 'all/allfiles' Unknown media type in type 'uri/mms' Unknown media type in type 'uri/mmst' Unknown media type in type 'uri/mmsu' Unknown media type in type 'uri/pnm' Unknown media type in type 'uri/rtspt' Unknown media type in type 'uri/rtspu' Processing triggers for bamfdaemon ... Rebuilding /usr/share/applications/bamf.index... Processing triggers for desktop-file-utils ... Processing triggers for gnome-menus ... Errors were encountered while processing: openoffice.org3.4-debian-menus_3.4-9593_all.deb Can anyone solve the problem?

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  • Load different levels in XML

    - by Anearion
    my question is more about a theoretical gener than a pratical way to make things happen. I'm about start developing a game for android, text based so i won't need sprites or animation, nor a game engine. Let's say is similar to a sudoku game, where each level is an harder version of sudoku and each level has some question to be asnwered over the sudoku itself. I was wondering if the better way is to have only one XML and then inside all the different levels, each one with his meta-tags, or if the different approach of making n xml files where each one is a level is preferred. At the moment a level should have those tags: <level> <question>Question_1</question> <hint1>what does it do?</hint1> <hint2>where...</hint2> .... <hintN>how...</hintN> </level> So each level could have some items to read and that's what made me think that maybe different files are better cuz if i have to load lvl 10 i can read only the 10.xml file. I hope my question isn't too stupind. Thanks in advance

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  • Problem displaying tiles using tiled map loader with SFML

    - by user1905192
    I've been searching fruitlessly for what I did wrong for the past couple of days and I was wondering if anyone here could help me. My program loads my tile map, but then crashes with an assertion error. The program breaks at this line: spacing = atoi(tilesetElement-Attribute("spacing")); Here's my main game.cpp file. #include "stdafx.h" #include "Game.h" #include "Ball.h" #include "level.h" using namespace std; Game::Game() { gameState=NotStarted; ball.setPosition(500,500); level.LoadFromFile("meow.tmx"); } void Game::Start() { if (gameState==NotStarted) { window.create(sf::VideoMode(1024,768,320),"game"); view.reset(sf::FloatRect(0,0,1000,1000));//ball drawn at 500,500 level.SetDrawingBounds(sf::FloatRect(view.getCenter().x-view.getSize().x/2,view.getCenter().y-view.getSize().y/2,view.getSize().x, view.getSize().y)); window.setView(view); gameState=Playing; } while(gameState!=Exiting) { GameLoop(); } window.close(); } void Game::GameLoop() { sf::Event CurrentEvent; window.pollEvent(CurrentEvent); switch(gameState) { case Playing: { window.clear(sf::Color::White); window.setView(view); if (CurrentEvent.type==sf::Event::Closed) { gameState=Exiting; } if ( !ball.IsFalling() &&!ball.IsJumping() &&sf::Keyboard::isKeyPressed(sf::Keyboard::Space)) { ball.setJState(); } ball.Update(view); level.Draw(window); ball.Draw(window); window.display(); break; } } } And here's the file where the error happens: /********************************************************************* Quinn Schwab 16/08/2010 SFML Tiled Map Loader The zlib license has been used to make this software fully compatible with SFML. See http://www.sfml-dev.org/license.php This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: 1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. 2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. 3. This notice may not be removed or altered from any source distribution. *********************************************************************/ #include "level.h" #include <iostream> #include "tinyxml.h" #include <fstream> int Object::GetPropertyInt(std::string name) { int i; i = atoi(properties[name].c_str()); return i; } float Object::GetPropertyFloat(std::string name) { float f; f = strtod(properties[name].c_str(), NULL); return f; } std::string Object::GetPropertyString(std::string name) { return properties[name]; } Level::Level() { //ctor } Level::~Level() { //dtor } using namespace std; bool Level::LoadFromFile(std::string filename) { TiXmlDocument levelFile(filename.c_str()); if (!levelFile.LoadFile()) { std::cout << "Loading level \"" << filename << "\" failed." << std::endl; return false; } //Map element. This is the root element for the whole file. TiXmlElement *map; map = levelFile.FirstChildElement("map"); //Set up misc map properties. width = atoi(map->Attribute("width")); height = atoi(map->Attribute("height")); tileWidth = atoi(map->Attribute("tilewidth")); tileHeight = atoi(map->Attribute("tileheight")); //Tileset stuff TiXmlElement *tilesetElement; tilesetElement = map->FirstChildElement("tileset"); firstTileID = atoi(tilesetElement->Attribute("firstgid")); spacing = atoi(tilesetElement->Attribute("spacing")); margin = atoi(tilesetElement->Attribute("margin")); //Tileset image TiXmlElement *image; image = tilesetElement->FirstChildElement("image"); std::string imagepath = image->Attribute("source"); if (!tilesetImage.loadFromFile(imagepath))//Load the tileset image { std::cout << "Failed to load tile sheet." << std::endl; return false; } tilesetImage.createMaskFromColor(sf::Color(255, 0, 255)); tilesetTexture.loadFromImage(tilesetImage); tilesetTexture.setSmooth(false); //Columns and rows (of tileset image) int columns = tilesetTexture.getSize().x / tileWidth; int rows = tilesetTexture.getSize().y / tileHeight; std::vector <sf::Rect<int> > subRects;//container of subrects (to divide the tilesheet image up) //tiles/subrects are counted from 0, left to right, top to bottom for (int y = 0; y < rows; y++) { for (int x = 0; x < columns; x++) { sf::Rect <int> rect; rect.top = y * tileHeight; rect.height = y * tileHeight + tileHeight; rect.left = x * tileWidth; rect.width = x * tileWidth + tileWidth; subRects.push_back(rect); } } //Layers TiXmlElement *layerElement; layerElement = map->FirstChildElement("layer"); while (layerElement) { Layer layer; if (layerElement->Attribute("opacity") != NULL)//check if opacity attribute exists { float opacity = strtod(layerElement->Attribute("opacity"), NULL);//convert the (string) opacity element to float layer.opacity = 255 * opacity; } else { layer.opacity = 255;//if the attribute doesnt exist, default to full opacity } //Tiles TiXmlElement *layerDataElement; layerDataElement = layerElement->FirstChildElement("data"); if (layerDataElement == NULL) { std::cout << "Bad map. No layer information found." << std::endl; } TiXmlElement *tileElement; tileElement = layerDataElement->FirstChildElement("tile"); if (tileElement == NULL) { std::cout << "Bad map. No tile information found." << std::endl; return false; } int x = 0; int y = 0; while (tileElement) { int tileGID = atoi(tileElement->Attribute("gid")); int subRectToUse = tileGID - firstTileID;//Work out the subrect ID to 'chop up' the tilesheet image. if (subRectToUse >= 0)//we only need to (and only can) create a sprite/tile if there is one to display { sf::Sprite sprite;//sprite for the tile sprite.setTexture(tilesetTexture); sprite.setTextureRect(subRects[subRectToUse]); sprite.setPosition(x * tileWidth, y * tileHeight); sprite.setColor(sf::Color(255, 255, 255, layer.opacity));//Set opacity of the tile. //add tile to layer layer.tiles.push_back(sprite); } tileElement = tileElement->NextSiblingElement("tile"); //increment x, y x++; if (x >= width)//if x has "hit" the end (right) of the map, reset it to the start (left) { x = 0; y++; if (y >= height) { y = 0; } } } layers.push_back(layer); layerElement = layerElement->NextSiblingElement("layer"); } //Objects TiXmlElement *objectGroupElement; if (map->FirstChildElement("objectgroup") != NULL)//Check that there is atleast one object layer { objectGroupElement = map->FirstChildElement("objectgroup"); while (objectGroupElement)//loop through object layers { TiXmlElement *objectElement; objectElement = objectGroupElement->FirstChildElement("object"); while (objectElement)//loop through objects { std::string objectType; if (objectElement->Attribute("type") != NULL) { objectType = objectElement->Attribute("type"); } std::string objectName; if (objectElement->Attribute("name") != NULL) { objectName = objectElement->Attribute("name"); } int x = atoi(objectElement->Attribute("x")); int y = atoi(objectElement->Attribute("y")); int width = atoi(objectElement->Attribute("width")); int height = atoi(objectElement->Attribute("height")); Object object; object.name = objectName; object.type = objectType; sf::Rect <int> objectRect; objectRect.top = y; objectRect.left = x; objectRect.height = y + height; objectRect.width = x + width; if (objectType == "solid") { solidObjects.push_back(objectRect); } object.rect = objectRect; TiXmlElement *properties; properties = objectElement->FirstChildElement("properties"); if (properties != NULL) { TiXmlElement *prop; prop = properties->FirstChildElement("property"); if (prop != NULL) { while(prop) { std::string propertyName = prop->Attribute("name"); std::string propertyValue = prop->Attribute("value"); object.properties[propertyName] = propertyValue; prop = prop->NextSiblingElement("property"); } } } objects.push_back(object); objectElement = objectElement->NextSiblingElement("object"); } objectGroupElement = objectGroupElement->NextSiblingElement("objectgroup"); } } else { std::cout << "No object layers found..." << std::endl; } return true; } Object Level::GetObject(std::string name) { for (int i = 0; i < objects.size(); i++) { if (objects[i].name == name) { return objects[i]; } } } void Level::SetDrawingBounds(sf::Rect<float> bounds) { drawingBounds = bounds; cout<<tileHeight; //Adjust the rect so that tiles are drawn just off screen, so you don't see them disappearing. drawingBounds.top -= tileHeight; drawingBounds.left -= tileWidth; drawingBounds.width += tileWidth; drawingBounds.height += tileHeight; } void Level::Draw(sf::RenderWindow &window) { for (int layer = 0; layer < layers.size(); layer++) { for (int tile = 0; tile < layers[layer].tiles.size(); tile++) { if (drawingBounds.contains(layers[layer].tiles[tile].getPosition().x, layers[layer].tiles[tile].getPosition().y)) { window.draw(layers[layer].tiles[tile]); } } } } I really hope that one of you can help me and I'm sorry if I've made any formatting issues. Thanks!

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  • Query a Log4Net-database

    - by pinhack
    So if you use Log4Net to log into a database (i.e. using the AdoNetAppender), how can you conveniently get an overview of what has happend ? Well, you could try the following Query ( T-SQL ):   SELECT convert(varchar(10),LogDB.Date,121) as Datum, LogDB.Level, LogDB.Logger,COUNT(LogDB.Logger) as Counter From Log4Net.dbo.Log as LogDB  where Level <> 'DEBUG' AND convert(varchar(10),LogDB.Date,121) like '2010-03-25' GROUP BY convert(varchar(10),LogDB.Date,121),LogDB.Level,LogDB.Logger ORDER BY counter desc This query will give you the number of events by the Logger at a specified date - and it's easy to customize, just adjust the Date and the Level to your needs. You need a bit more information than that? How about this query:  Select  convert(varchar(10),LogDB.Date,121) as Datum,LogDB.Level,LogDB.Message,LogDB.Logger ,count(LogDB.Message) as counter From Log4Net.dbo.Log as LogDB where Level <> 'DEBUG' AND convert(varchar(10),LogDB.Date,121) like '2010-03-25' GROUP BY convert(varchar(10),LogDB.Date,121),LogDB.Level,LogDB.Message,LogDB.Logger ORDER BY counter desc Similar to the first one, but inclusive the Message - which will return a much larger resultset.

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  • Inside the DLR – Invoking methods

    - by Simon Cooper
    So, we’ve looked at how a dynamic call is represented in a compiled assembly, and how the dynamic lookup is performed at runtime. The last piece of the puzzle is how the resolved method gets invoked, and that is the subject of this post. Invoking methods As discussed in my previous posts, doing a full lookup and bind at runtime each and every single time the callsite gets invoked would be far too slow to be usable. The results obtained from the callsite binder must to be cached, along with a series of conditions to determine whether the cached result can be reused. So, firstly, how are the conditions represented? These conditions can be anything; they are determined entirely by the semantics of the language the binder is representing. The binder has to be able to return arbitary code that is then executed to determine whether the conditions apply or not. Fortunately, .NET 4 has a neat way of representing arbitary code that can be easily combined with other code – expression trees. All the callsite binder has to return is an expression (called a ‘restriction’) that evaluates to a boolean, returning true when the restriction passes (indicating the corresponding method invocation can be used) and false when it does’t. If the bind result is also represented in an expression tree, these can be combined easily like so: if ([restriction is true]) { [invoke cached method] } Take my example from my previous post: public class ClassA { public static void TestDynamic() { CallDynamic(new ClassA(), 10); CallDynamic(new ClassA(), "foo"); } public static void CallDynamic(dynamic d, object o) { d.Method(o); } public void Method(int i) {} public void Method(string s) {} } When the Method(int) method is first bound, along with an expression representing the result of the bind lookup, the C# binder will return the restrictions under which that bind can be reused. In this case, it can be reused if the types of the parameters are the same: if (thisArg.GetType() == typeof(ClassA) && arg1.GetType() == typeof(int)) { thisClassA.Method(i); } Caching callsite results So, now, it’s up to the callsite to link these expressions returned from the binder together in such a way that it can determine which one from the many it has cached it should use. This caching logic is all located in the System.Dynamic.UpdateDelegates class. It’ll help if you’ve got this type open in a decompiler to have a look yourself. For each callsite, there are 3 layers of caching involved: The last method invoked on the callsite. All methods that have ever been invoked on the callsite. All methods that have ever been invoked on any callsite of the same type. We’ll cover each of these layers in order Level 1 cache: the last method called on the callsite When a CallSite<T> object is first instantiated, the Target delegate field (containing the delegate that is called when the callsite is invoked) is set to one of the UpdateAndExecute generic methods in UpdateDelegates, corresponding to the number of parameters to the callsite, and the existance of any return value. These methods contain most of the caching, invoke, and binding logic for the callsite. The first time this method is invoked, the UpdateAndExecute method finds there aren’t any entries in the caches to reuse, and invokes the binder to resolve a new method. Once the callsite has the result from the binder, along with any restrictions, it stitches some extra expressions in, and replaces the Target field in the callsite with a compiled expression tree similar to this (in this example I’m assuming there’s no return value): if ([restriction is true]) { [invoke cached method] return; } if (callSite._match) { _match = false; return; } else { UpdateAndExecute(callSite, arg0, arg1, ...); } Woah. What’s going on here? Well, this resulting expression tree is actually the first level of caching. The Target field in the callsite, which contains the delegate to call when the callsite is invoked, is set to the above code compiled from the expression tree into IL, and then into native code by the JIT. This code checks whether the restrictions of the last method that was invoked on the callsite (the ‘primary’ method) match, and if so, executes that method straight away. This means that, the next time the callsite is invoked, the first code that executes is the restriction check, executing as native code! This makes this restriction check on the primary cached delegate very fast. But what if the restrictions don’t match? In that case, the second part of the stitched expression tree is executed. What this section should be doing is calling back into the UpdateAndExecute method again to resolve a new method. But it’s slightly more complicated than that. To understand why, we need to understand the second and third level caches. Level 2 cache: all methods that have ever been invoked on the callsite When a binder has returned the result of a lookup, as well as updating the Target field with a compiled expression tree, stitched together as above, the callsite puts the same compiled expression tree in an internal list of delegates, called the rules list. This list acts as the level 2 cache. Why use the same delegate? Stitching together expression trees is an expensive operation. You don’t want to do it every time the callsite is invoked. Ideally, you would create one expression tree from the binder’s result, compile it, and then use the resulting delegate everywhere in the callsite. But, if the same delegate is used to invoke the callsite in the first place, and in the caches, that means each delegate needs two modes of operation. An ‘invoke’ mode, for when the delegate is set as the value of the Target field, and a ‘match’ mode, used when UpdateAndExecute is searching for a method in the callsite’s cache. Only in the invoke mode would the delegate call back into UpdateAndExecute. In match mode, it would simply return without doing anything. This mode is controlled by the _match field in CallSite<T>. The first time the callsite is invoked, _match is false, and so the Target delegate is called in invoke mode. Then, if the initial restriction check fails, the Target delegate calls back into UpdateAndExecute. This method sets _match to true, then calls all the cached delegates in the rules list in match mode to try and find one that passes its restrictions, and invokes it. However, there needs to be some way for each cached delegate to inform UpdateAndExecute whether it passed its restrictions or not. To do this, as you can see above, it simply re-uses _match, and sets it to false if it did not pass the restrictions. This allows the code within each UpdateAndExecute method to check for cache matches like so: foreach (T cachedDelegate in Rules) { callSite._match = true; cachedDelegate(); // sets _match to false if restrictions do not pass if (callSite._match) { // passed restrictions, and the cached method was invoked // set this delegate as the primary target to invoke next time callSite.Target = cachedDelegate; return; } // no luck, try the next one... } Level 3 cache: all methods that have ever been invoked on any callsite with the same signature The reason for this cache should be clear – if a method has been invoked through a callsite in one place, then it is likely to be invoked on other callsites in the codebase with the same signature. Rather than living in the callsite, the ‘global’ cache for callsite delegates lives in the CallSiteBinder class, in the Cache field. This is a dictionary, typed on the callsite delegate signature, providing a RuleCache<T> instance for each delegate signature. This is accessed in the same way as the level 2 callsite cache, by the UpdateAndExecute methods. When a method is matched in the global cache, it is copied into the callsite and Target cache before being executed. Putting it all together So, how does this all fit together? Like so (I’ve omitted some implementation & performance details): That, in essence, is how the DLR performs its dynamic calls nearly as fast as statically compiled IL code. Extensive use of expression trees, compiled to IL and then into native code. Multiple levels of caching, the first of which executes immediately when the dynamic callsite is invoked. And a clever re-use of compiled expression trees that can be used in completely different contexts without being recompiled. All in all, a very fast and very clever reflection caching mechanism.

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  • Alternatives to Pessimistic Locking in Cluster Applications

    - by amphibient
    I am researching alternatives to database-level pessimistic locking to achieve transaction isolation in a cluster of Java applications going against the same database. Synchronizing concurrent access in the application tier is clearly not a solution in the present configuration because the same database transaction can be invoked from multiple JVMs concurrently. Currently, we are subject to occasional race conditions which, due to the optimistic locking we have in place via Hibernate, cause a StaleObjectStateException exception and data loss. I have a moderately large transaction within the scope of my refactoring project. Let's describe it as updating one top-level table row and then making various related inserts and/or updates to several of its child entities. I would like to insure exclusive access to the top-level table row and all of the children to be affected but I would like to stay away from pessimistic locking at the database level for performance reasons mostly. We use Hibernate for ORM. Does it make sense to start a single (perhaps synchronous) message queue application into which this method could be moved to insure synchronized access as opposed to each cluster node using its own, which is a clear race condition hazard? I am mentioning this approach even though I am not confident in it because both the top-level table row and its children could also be updated from other system calls, not just the mentioned transaction. So I am seeking to design a solution where the top-level table row and its children will all somehow be pseudo-locked (exclusive transaction isolation) but at the application and not the database level. I am open to ideas and suggestions, I understand this is not a very cut and dried challenge.

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  • How to cache authentication in Linux using PAM/Kerberos authentication (for CVS)?

    - by Calonthar
    We have several Linux servers that authenticate Linux user passwords on our Windows Active Directory Server using PAM and Kerberos 5. The Linux distro we use is CentOS 6. On one system, we have several Version Control Systems like CVS and Subversion, both of which authenticate users throug PAM, such that users can use their normal Unix resp. Windows AD accounts. Since we started using Kerberos for password authentication, we experienced that CVS on a client machine is often much slower in establishing a connection. CVS authenticates the user on every request (eg. cvs diff, log, update...). Is is possible to cache the credentials that kerberos uses, sucht that is does not need to ask the Windows AD server every time a user executes a cvs action? Our PAM config /etc/pam.d/system-auth looks like the following: auth required pam_env.so auth sufficient pam_unix.so nullok try_first_pass auth requisite pam_succeed_if.so uid >= 500 quiet auth sufficient pam_krb5.so use_first_pass auth required pam_deny.so account required pam_unix.so broken_shadow account sufficient pam_succeed_if.so uid < 500 quiet account [default=bad success=ok user_unknown=ignore] pam_krb5.so account required pam_permit.so password requisite pam_cracklib.so try_first_pass retry=3 password sufficient pam_unix.so md5 shadow nullok try_first_pass use_authtok password sufficient pam_krb5.so use_authtok password required pam_deny.so session optional pam_keyinit.so revoke session required pam_limits.so session [success=1 default=ignore] pam_succeed_if.so service in crond quiet use_uid session required pam_unix.so session optional pam_krb5.so

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  • Strange issue ! Local network cache of PHP and Apache2 on Win Server 2008 R2

    - by Ahmed Benlahsen
    Software configuration : I have a new Server with windows server 2008 R2 installed via VMWare. I have installed Apache2.2, PHP5.2 and MySQL5.5 as separated packages. Issue : On my first installation of my application all works great. When I updated some JS and CSS files then I access to my application again from a PC on local network I get the old JS and CSS versions! But when I access to the same application on local server I got the latest versions of those files! Link of my application on local server is : http://localhost/BADIL Link of my application from local network is : http://LOCAL_SERVER_IP/BADIL I never had this kind of issue! I think that there are some cache but I don't know where! Maybe on Win Server 2008 R2 or on VMWare ! The question is : Why when I access to my application on the server all works fine, but when I access to the same application from a local network I have the old version of JS and CSS files?? Any one can help me please?! Regards.

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  • How do I get yum to see updates to a local repo without cleaning cache?

    - by Matt
    I have set up a local yum repository which I use to install test builds. For the testing purposes, my packages are versioned by <svn version number>.<date>.<time> (e.g. 12345.20110908.150404 The trouble is, once I make a new RPM, copy it to the repository directory and run createrepo $REPO_DIR, yum does not see the new RPM as being available. $ cd $REPO_DIR $ ls -1 repodata package-12345.20110908.150404-1.x86_64.rpm package-12345.20110908.174329-1.x86_64.rpm $ createrepo . # ...snip... $ rpm -q package package-12345.20110908.150404-1.x86_64 $ yum list --showduplicates package Installed Packages package.x86_64 12345.20110908.150404-1 @repo Available Packages package.x86_64 12345.20110908.150404-1 repo I can see the updates and grab them if I run yum clean all and then re-fetch the metadata, but I think this just means I need to be doing something else from the repo, as I don't have to do that for other yum repos. How do I need to set up my local repository so that I only need to run yum update from the client without having to clean my yum cache?

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  • Non-volatile cache RAID controllers: what kind of protection is there against NVCACHE failure?

    - by astrostl
    The battery back-up (BBU) model: admin enables write-back cache with BBU writes are cached to the RAID controller's RAM (major performance benefit) the battery saves uncommitted and cached data in the event of a power loss (reliability) If I lose power and come back within a day or so, my data should be both complete and uncorrupted. The downside to this is that, if the battery is dead or low, OR EVEN IF IT IS IN A RELEARN CYCLE (drain/charge loops to ensure the battery's health), the controller reverts to write-through mode and performance will suffer. What's more, the relearn cycles are usually automated on a schedule which may or may not happen in the middle of big traffic. So, that has to be manually disabled and manually scheduled for off-hours if it's a concern. Annoying either way. NV caches have capacitors with a sufficient charge to commit any uncommitted-to-disk data to flash. Not only is that more survivable in longer loss situations, but you don't have to concern yourself with battery death, wear-out, or relearning. All of that sounds great to me. What doesn't sound great to me is the prospect of that flash module having an issue, though. What if it's completely hosed? What if it's only partially hosed? A bit corrupted at the edges? Relearn cycles can tell when something like a simple battery is failing, but is there a similar process to verify that the flash is functional? I'm just far more trusting of a battery, warts and all. I know the card's RAM can fail, the card itself can fail - that's common territory, though. In case you didn't guess, yeah, I've experienced a shocking-to-me amount of flash/SSD/etc. failure :)

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  • SQL SERVER – Simple Example of Snapshot Isolation – Reduce the Blocking Transactions

    - by pinaldave
    To learn any technology and move to a more advanced level, it is very important to understand the fundamentals of the subject first. Today, we will be talking about something which has been quite introduced a long time ago but not properly explored when it comes to the isolation level. Snapshot Isolation was introduced in SQL Server in 2005. However, the reality is that there are still many software shops which are using the SQL Server 2000, and therefore cannot be able to maintain the Snapshot Isolation. Many software shops have upgraded to the later version of the SQL Server, but their respective developers have not spend enough time to upgrade themselves with the latest technology. “It works!” is a very common answer of many when they are asked about utilizing the new technology, instead of backward compatibility commands. In one of the recent consultation project, I had same experience when developers have “heard about it” but have no idea about snapshot isolation. They were thinking it is the same as Snapshot Replication – which is plain wrong. This is the same demo I am including here which I have created for them. In Snapshot Isolation, the updated row versions for each transaction are maintained in TempDB. Once a transaction has begun, it ignores all the newer rows inserted or updated in the table. Let us examine this example which shows the simple demonstration. This transaction works on optimistic concurrency model. Since reading a certain transaction does not block writing transaction, it also does not block the reading transaction, which reduced the blocking. First, enable database to work with Snapshot Isolation. Additionally, check the existing values in the table from HumanResources.Shift. ALTER DATABASE AdventureWorks SET ALLOW_SNAPSHOT_ISOLATION ON GO SELECT ModifiedDate FROM HumanResources.Shift GO Now, we will need two different sessions to prove this example. First Session: Set Transaction level isolation to snapshot and begin the transaction. Update the column “ModifiedDate” to today’s date. -- Session 1 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN UPDATE HumanResources.Shift SET ModifiedDate = GETDATE() GO Please note that we have not yet been committed to the transaction. Now, open the second session and run the following “SELECT” statement. Then, check the values of the table. Please pay attention on setting the Isolation level for the second one as “Snapshot” at the same time when we already start the transaction using BEGIN TRAN. -- Session 2 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN SELECT ModifiedDate FROM HumanResources.Shift GO You will notice that the values in the table are still original values. They have not been modified yet. Once again, go back to session 1 and begin the transaction. -- Session 1 COMMIT After that, go back to Session 2 and see the values of the table. -- Session 2 SELECT ModifiedDate FROM HumanResources.Shift GO You will notice that the values are yet not changed and they are still the same old values which were there right in the beginning of the session. Now, let us commit the transaction in the session 2. Once committed, run the same SELECT statement once more and see what the result is. -- Session 2 COMMIT SELECT ModifiedDate FROM HumanResources.Shift GO You will notice that it now reflects the new updated value. I hope that this example is clear enough as it would give you good idea how the Snapshot Isolation level works. There is much more to write about an extra level, READ_COMMITTED_SNAPSHOT, which we will be discussing in another post soon. If you wish to use this transaction’s Isolation level in your production database, I would appreciate your comments about their performance on your servers. I have included here the complete script used in this example for your quick reference. ALTER DATABASE AdventureWorks SET ALLOW_SNAPSHOT_ISOLATION ON GO SELECT ModifiedDate FROM HumanResources.Shift GO -- Session 1 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN UPDATE HumanResources.Shift SET ModifiedDate = GETDATE() GO -- Session 2 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN SELECT ModifiedDate FROM HumanResources.Shift GO -- Session 1 COMMIT -- Session 2 SELECT ModifiedDate FROM HumanResources.Shift GO -- Session 2 COMMIT SELECT ModifiedDate FROM HumanResources.Shift GO Reference: Pinal Dave (http://blog.sqlauthority.com) Filed under: Pinal Dave, SQL, SQL Authority, SQL Performance, SQL Query, SQL Scripts, SQL Server, SQL Tips and Tricks, T SQL, Technology Tagged: Transaction Isolation

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  • SQL SERVER – Simple Example of Snapshot Isolation – Reduce the Blocking Transactions

    - by pinaldave
    To learn any technology and move to a more advanced level, it is very important to understand the fundamentals of the subject first. Today, we will be talking about something which has been quite introduced a long time ago but not properly explored when it comes to the isolation level. Snapshot Isolation was introduced in SQL Server in 2005. However, the reality is that there are still many software shops which are using the SQL Server 2000, and therefore cannot be able to maintain the Snapshot Isolation. Many software shops have upgraded to the later version of the SQL Server, but their respective developers have not spend enough time to upgrade themselves with the latest technology. “It works!” is a very common answer of many when they are asked about utilizing the new technology, instead of backward compatibility commands. In one of the recent consultation project, I had same experience when developers have “heard about it” but have no idea about snapshot isolation. They were thinking it is the same as Snapshot Replication – which is plain wrong. This is the same demo I am including here which I have created for them. In Snapshot Isolation, the updated row versions for each transaction are maintained in TempDB. Once a transaction has begun, it ignores all the newer rows inserted or updated in the table. Let us examine this example which shows the simple demonstration. This transaction works on optimistic concurrency model. Since reading a certain transaction does not block writing transaction, it also does not block the reading transaction, which reduced the blocking. First, enable database to work with Snapshot Isolation. Additionally, check the existing values in the table from HumanResources.Shift. ALTER DATABASE AdventureWorks SET ALLOW_SNAPSHOT_ISOLATION ON GO SELECT ModifiedDate FROM HumanResources.Shift GO Now, we will need two different sessions to prove this example. First Session: Set Transaction level isolation to snapshot and begin the transaction. Update the column “ModifiedDate” to today’s date. -- Session 1 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN UPDATE HumanResources.Shift SET ModifiedDate = GETDATE() GO Please note that we have not yet been committed to the transaction. Now, open the second session and run the following “SELECT” statement. Then, check the values of the table. Please pay attention on setting the Isolation level for the second one as “Snapshot” at the same time when we already start the transaction using BEGIN TRAN. -- Session 2 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN SELECT ModifiedDate FROM HumanResources.Shift GO You will notice that the values in the table are still original values. They have not been modified yet. Once again, go back to session 1 and begin the transaction. -- Session 1 COMMIT After that, go back to Session 2 and see the values of the table. -- Session 2 SELECT ModifiedDate FROM HumanResources.Shift GO You will notice that the values are yet not changed and they are still the same old values which were there right in the beginning of the session. Now, let us commit the transaction in the session 2. Once committed, run the same SELECT statement once more and see what the result is. -- Session 2 COMMIT SELECT ModifiedDate FROM HumanResources.Shift GO You will notice that it now reflects the new updated value. I hope that this example is clear enough as it would give you good idea how the Snapshot Isolation level works. There is much more to write about an extra level, READ_COMMITTED_SNAPSHOT, which we will be discussing in another post soon. If you wish to use this transaction’s Isolation level in your production database, I would appreciate your comments about their performance on your servers. I have included here the complete script used in this example for your quick reference. ALTER DATABASE AdventureWorks SET ALLOW_SNAPSHOT_ISOLATION ON GO SELECT ModifiedDate FROM HumanResources.Shift GO -- Session 1 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN UPDATE HumanResources.Shift SET ModifiedDate = GETDATE() GO -- Session 2 SET TRANSACTION ISOLATION LEVEL SNAPSHOT BEGIN TRAN SELECT ModifiedDate FROM HumanResources.Shift GO -- Session 1 COMMIT -- Session 2 SELECT ModifiedDate FROM HumanResources.Shift GO -- Session 2 COMMIT SELECT ModifiedDate FROM HumanResources.Shift GO Reference: Pinal Dave (http://blog.sqlauthority.com) Filed under: Pinal Dave, SQL, SQL Authority, SQL Performance, SQL Query, SQL Scripts, SQL Server, SQL Tips and Tricks, T SQL, Technology Tagged: Transaction Isolation

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  • Manually filling opcode cache for entire app using apc_compile_file, then switching to new release.

    - by Ben
    Does anyone have a great system, or any ideas, for doing as the title says? I want to switch production version of web app-- written in PHP and served by Apache-- from release 1234 to release 1235, but before that happens, have all files already in the opcode cache (APC). Then after the switch, remove the old cache entries for files from release 1234. As far as I can think of there are three easy ways of atomically switching from one version to the next. Have a symbolic link, for example /live, that is always the document root but is changed to point from one version to the next. Similarly, have a directory /live that is always the document root, but use mv live oldversion && mv newversion live to switch to new version. Edit apache configuration to change the document root to newversion, then restart apache. I think it is preferable not to have to do 3, but I can't think of anyway to precompile all php files AND use 1 or 2 to switch release. So can someone either convince me its okay to rely on option 3, or tell me how to work with 1 or 2, or reveal some other option I am not thinking of?

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  • Does IE completely ignore cache control headers for AJAX requests?

    - by Joshua Hayworth
    Hello there, I've got, what I would consider, a simple test web site. A single page with a single button. Here is a copy of the source I'm working with if you would like to download it and play with it. When that button is clicked, it creates a JavaScript timer that executes once a second. When the timer function is executed, An AJAX call is made to retrieve a text value. That text value is then placed into the DOM. What's my problem? IE Caching. Crack open Task Manager and watch what happens to the iexplorer.exe process (IE 8.0.7600.16385 for me) while the timer in that page is executing. See the memory and handle count getting larger? Why is that happening when, by all accounts, I have caching turned off. I've got the jQuery cache option set to false in $.ajaxSetup. I've got the CacheControl header set to no-cache and no-store. The Expires header is set to DateTime.Now.AddDays(-1). The headers are set in both the page code-behind as well as the HTTP Handler's response. Anybody got any ideas as to how I could prevent IE from caching the results of the AJAX call? Here is what the iexplorer.exe process looks like in ProcessMonitor. I believe that the activity shown in this picture is exactly what I'm attempting to prevent.

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  • Two different sites, same IP, same top-level domain, on IIS 7.5 -- one works and the other displays HTTP 404 error

    - by user717236
    I'm running a Windows 2008 R2 box with IIS 7.5 as the web server. On IIS, I have two websites: mysubsite1.mysite.com and mysubsite2.mysite.com. There is only one IP on the server and both sites share this IP. Here is how I have the bindings configured: mysubsite1.mysite.com works fine. However, mysubsite2.mysite.com gives me the following error: Not Found HTTP Error 404. The requested resource is not found. Now, if I change the Host name field for mysubsite1.mysite.com to blank and restart the web server, both sites work! The question is why is the host name field for the first site causing an HTTP 404 error for the second site when both sites' Host name fields are filled? I would appreciate any insight. Thank you.

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  • How much HDD space would I need to cache the web while respecting robot.txts?

    - by Koning Baard XIV
    I want to experiment with creating a web crawler. I'll start with indexing a few medium sized website like Stack Overflow or Smashing Magazine. If it works, I'd like to start crawling the entire web. I'll respect robot.txts. I save all html, pdf, word, excel, powerpoint, keynote, etc... documents (not exes, dmgs etc, just documents) in a MySQL DB. Next to that, I'll have a second table containing all restults and descriptions, and a table with words and on what page to find those words (aka an index). How much HDD space do you think I need to save all the pages? Is it as low as 1 TB or is it about 10 TB, 20? Maybe 30? 1000? Thanks

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  • What privilege level is required on a Windows client workstation on an ActiveDomain to break file lo

    - by Mike Burton
    I'm not sure if I should be asking this here or on StackOverflow, but here goes: I'm part of a team maintaining a document management application, and I'm trying to figure out Windows file locking permissions. We use a utility somebody downloaded years ago called psunlock to remotely close all locks on a file. We recently discovered that this does not work across different domains on our VPN. A little bit of digging lead me to the samba manual's discussion of file locking. I still don't really "get it", though. Does anyone have any insight to share into how the process of locking and breaking locks on files works in a network context? My thinking is that privileges are required both on the file appliance and on the client workstations which hold locks. Is that accurate? Can anyone give a more specific version? Ideally I'm looking for something along the lines of A user must have privilege level X in order to break locks held from a client workstation. In practice I'd be happy with a hotlink to a good white paper on the subject.

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