Verilog errors during synthesis
- by chester.boo
Here is the code in question:
http://pastebin.com/smqUNpdt
When I do a syntax check, everything is okay. But when I try to synthesize with XST I get the following errors:
ERROR:Xst:870 - "fibonacci.v" line 42: Can not simplify operator DIV.
ERROR:Xst:899 - "fibonacci.v" line 29: The logic for <out> does not match a known FF or Latch template.
ERROR:Xst:899 - "fibonacci.v" line 30: The logic for <ratio> does not match a known FF or Latch template.
ERROR:Xst:899 - "fibonacci.v" line 36: The logic for <nextstate> does not match a known FF or Latch template.
ERROR:Xst:899 - "fibonacci.v" line 37: The logic for <previousstate> does not match a known FF or Latch template.
ERROR:Xst:899 - "fibonacci.v" line 38: The logic for <presentstate> does not match a known FF or Latch template.
ERROR:Xst:899 - "fibonacci.v" line 39: The logic for <fib_number_cnt> does not match a known FF or Latch template.