Search Results

Search found 24498 results on 980 pages for 'lock pages in memory'.

Page 212/980 | < Previous Page | 208 209 210 211 212 213 214 215 216 217 218 219  | Next Page >

  • What causes Multi-Page allocations?

    - by SQLOS Team
    Writing about changes in the Denali Memory Manager In his last post Rusi mentioned: " In previous SQL versions only the 8k allocations were limited by the ‘max server memory’ configuration option.  Allocations larger than 8k weren’t constrained." In SQL Server versions before Denali single page allocations and multi-Page allocations are handled by different components, the Single Page Allocator (which is responsible for Buffer Pool allocations and governed by 'max server memory') and the Multi-Page allocator (MPA) which handles allocations of greater than an 8K page. If there are many multi-page allocations this can affect how much memory needs to be reserved outside 'max server memory' which may in turn involve setting the -g memory_to_reserve startup parameter. We'll follow up with more generic articles on the new Memory Manager structure, but in this post I want to clarify what might cause these larger allocations. So what kinds of query result in MPA activity? I was asked this question the other day after delivering an MCM webcast on Memory Manager changes in Denali. After asking around our Dev team I was connected to one of our test leads Sangeetha who had tested the plan cache, and kindly provided this example of an MPA intensive query: A workload that has stored procedures with a large # of parameters (say > 100, > 500), and then invoked via large ad hoc batches, where each SP has different parameters will result in a plan being cached for this “exec proc” batch. This plan will result in MPA.   Exec proc_name @p1, ….@p500 Exec proc_name @p1, ….@p500 . . . Exec proc_name @p1, ….@p500 Go   Another workload would be large adhoc batches of the form: Select * from t where col1 in (1, 2, 3, ….500) Select * from t where col1 in (1, 2, 3, ….500) Select * from t where col1 in (1, 2, 3, ….500) … Go  In Denali all page allocations are handled by an "Any size page allocator" and included in 'max server memory'. The buffer pool effectively becomes a client of the any size page allocator, which in turn relies on the memory manager. - Guy Originally posted at http://blogs.msdn.com/b/sqlosteam/

    Read the article

  • Duplicate domain names - .net and .com Create separate pages, or redirect?

    - by guisasso
    In a SEO point of view: This website has a good amount of traffic for a local business, but also ships some merchandise. While the .net domain (registered first) is associated with the local busines (google places, maps, etc...) the .com domain only redirects to the .net domain. Is it good, bad or okay to create a different page for the domain .com for example, that would be pretty simple, but would link to the 10 different categories of products that this company sells? I know links are good, so there's that, but what else is good, or bad? Thanks in advance!

    Read the article

  • How to use rel=canonical with Sitecore aliases?

    - by Mike G
    I have inherited a Sitecore architecture that is a mess from an SEO duplicate content POV. There are multiple aliases that have been created (and indexed by the search engines) for many of the 2nd tier pages of the site. Due to server issues, I am not able to 301 redirect these duped pages, so I would like to use the rel=canonical tag in an attempt to try and get Google/Bing to recognize the correct pages I would like to appear in the index. I have blocked the most extraneous duped pages with a robots.txt file, however, since Google/Bing have already spidered many of the duped pages, I need to keep them accessible to the spiders, BUT removed from the index. The catch is, since the duped pages are aliases (and don't really physically exist in Sitecore that I can find), I am not sure how to go about using rel=canonical - or if I even can in this situation..?

    Read the article

  • Booting 11.10 from USB stick on MacBook Pro 5,1 fails

    - by Helge Stenström
    I've created a bootable memory stick on a Windows computer, and tested it on an HP PC. It's made from a 64-bit image of Ubuntu 11.10, downloaded from http://www.ubuntu.com/download/ubuntu/download. When I boot from this memory stick, there is some kind of boot menu, where I can choose to run Ubuntu from the memory stick, or install. I select Run from memory stick. (the words may be wrong here, I'm taking it from memory.) From this point, the screen is black (but backlighted), and I can't do anything but turn off the computer. It gets hot, too. Has anyone been more successful than me? Are there known issues? The computer is a 15 inch MacBook Pro 5,1 (unibody, late 2008), 4 GB memory.

    Read the article

  • Can I improve my AdWords quality scores with better landing pages?

    - by Eric
    I noticed that I have some keywords in my AdWords that are totally applicable to my site but the quality score of the keyword is 4 or 5. I'd like to get it up higher by creating custom versions of my site's home page (landing page) targeted specifically for people searching on those keywords. So for example, if we pretend my site sells pet food, my current home page has the phrase "dog food." I have a specific AdWords campaign for people searching on cat food (with cat food-specific ads). I'm thinking about changing the URL on those ads to something like http://mysite.com/cat.html, so a different home page comes up with the phrase "cat food." My thinking is that will help Google see that this new landing page is appropriate for the keywords and will raise my quality score for the "cat food" keywords. (Note that none of what I'm doing is shady or misleading; nobody would disagree that all of the keywords and ads I've created are perfect and appropriate for what my site offers.) Question: is what I describe the correct way to raise poor quality scores on keywords, and will it help?

    Read the article

  • Computer won't reboot without waiting for a while

    - by Benjamin
    I've got an unusual problem with my computer. When ever I reboot my computer it won't boot, I get a few beeps from the BIOS and nothing else, however if I wait for a few minuets the computer will boot perfectly. I tried to count the beeps and I get around 7-9 of them; the first two are noticeably closer together than the rest. [Edit: I'm now reasonably confident it's 1 long followed by 8 short beeps. That would be a display related issue: http://www.bioscentral.com/beepcodes/amibeep.htm] My BIOS is American Megatrends Inc and version P1.80, the Motherboard is an ASRock X58 Extreme (both according to dmidecode) Here's an output from LSPCI, I'm not sure what else might be useful but I can provide whatever's asked. 00:00.0 Host bridge: Intel Corporation 5520/5500/X58 I/O Hub to ESI Port (rev 13) 00:01.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 1 (rev 13) 00:03.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 3 (rev 13) 00:07.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 7 (rev 13) 00:14.0 PIC: Intel Corporation 5520/5500/X58 I/O Hub System Management Registers (rev 13) 00:14.1 PIC: Intel Corporation 5520/5500/X58 I/O Hub GPIO and Scratch Pad Registers (rev 13) 00:14.2 PIC: Intel Corporation 5520/5500/X58 I/O Hub Control Status and RAS Registers (rev 13) 00:14.3 PIC: Intel Corporation 5520/5500/X58 I/O Hub Throttle Registers (rev 13) 00:1a.0 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4 00:1a.1 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5 00:1a.2 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6 00:1a.7 USB controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 00:1b.0 Audio device: Intel Corporation 82801JI (ICH10 Family) HD Audio Controller 00:1c.0 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 1 00:1c.1 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 2 00:1c.5 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 6 00:1d.0 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1 00:1d.1 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2 00:1d.2 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3 00:1d.7 USB controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90) 00:1f.0 ISA bridge: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller 00:1f.2 SATA controller: Intel Corporation 82801JI (ICH10 Family) SATA AHCI Controller 00:1f.3 SMBus: Intel Corporation 82801JI (ICH10 Family) SMBus Controller 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 03) 02:00.0 FireWire (IEEE 1394): VIA Technologies, Inc. VT6315 Series Firewire Controller 02:00.1 IDE interface: VIA Technologies, Inc. VT6415 PATA IDE Host Controller (rev a0) 03:00.0 SATA controller: JMicron Technology Corp. JMB360 AHCI Controller (rev 02) 05:00.0 VGA compatible controller: nVidia Corporation GT200b [GeForce GTX 285] (rev a1) ff:00.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture Generic Non-Core Registers (rev 05) ff:00.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture System Address Decoder (rev 05) ff:02.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Link 0 (rev 05) ff:02.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Physical 0 (rev 05) ff:03.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller (rev 05) ff:03.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Target Address Decoder (rev 05) ff:03.4 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Test Registers (rev 05) ff:04.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Control Registers (rev 05) ff:04.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Address Registers (rev 05) ff:04.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Rank Registers (rev 05) ff:04.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Thermal Control Registers (rev 05) ff:05.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Control Registers (rev 05) ff:05.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Address Registers (rev 05) ff:05.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Rank Registers (rev 05) ff:05.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Thermal Control Registers (rev 05) ff:06.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Control Registers (rev 05) ff:06.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Address Registers (rev 05) ff:06.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Rank Registers (rev 05) ff:06.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Thermal Control Registers (rev 05) Update: ok I installed lm-sensors and here's the output. coretemp-isa-0000 Adapter: ISA adapter Core 0: +58.0°C (high = +80.0°C, crit = +100.0°C) Core 1: +59.0°C (high = +80.0°C, crit = +100.0°C) Core 2: +58.0°C (high = +80.0°C, crit = +100.0°C) Core 3: +57.0°C (high = +80.0°C, crit = +100.0°C) it8720-isa-0a10 Adapter: ISA adapter in0: +0.93 V (min = +0.00 V, max = +4.08 V) in1: +0.06 V (min = +0.00 V, max = +4.08 V) in2: +3.25 V (min = +0.00 V, max = +4.08 V) +5V: +2.91 V (min = +0.00 V, max = +4.08 V) in4: +3.04 V (min = +0.00 V, max = +4.08 V) in5: +2.94 V (min = +0.00 V, max = +4.08 V) in6: +2.14 V (min = +0.00 V, max = +4.08 V) 5VSB: +2.96 V (min = +0.00 V, max = +4.08 V) Vbat: +3.28 V fan1: 1869 RPM (min = 0 RPM) fan2: 0 RPM (min = 0 RPM) fan3: 0 RPM (min = 0 RPM) fan4: 1106 RPM (min = -1 RPM) fan5: 225000 RPM (min = -1 RPM) temp1: +39.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor temp2: +56.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor temp3: +127.0°C (low = +0.0°C, high = +127.0°C) sensor = thermistor cpu0_vid: +1.650 V intrusion0: ALARM If it helps here's the summery from sensors-detect Driver `it87': * ISA bus, address 0xa10 Chip `ITE IT8720F Super IO Sensors' (confidence: 9) Driver `adt7475': * Bus `NVIDIA i2c adapter 3 at 5:00.0' Busdriver `nvidia', I2C address 0x2e Chip `Analog Devices ADT7473' (confidence: 5) Driver `coretemp': * Chip `Intel digital thermal sensor' (confidence: 9)

    Read the article

  • Should I pass link juice to my pages on other websites that are already high PR domains?

    - by huzzah
    I am starting a new website for a local business and have entries listed for it on places like urbanspoon, yelp, google+ local, etc. I am thinking of listing these citation sites on my business website to encourage visitors of my site to go and review the business on those sites. If I dofollow I will pass link juice to my page on that site, but doesn't that mean that the very very little PR juice I have will be leached away from me? Is it better to nofollow them?

    Read the article

  • How do I interpret direct traffic that lands on random pages?

    - by mfg
    Looking at yesterday, according to Google Analytics, I got six direct visitors to my site (their source/medium is direct/(none)). Only one ended up at the actual domain. The other five ended up at miscellaneous foo.com/xyz.html. I did not send out links to people by email, and I'm not sure how likely it is the people would have copy/pasted the URLs. How do the visitors end up there? Is there a way to better capture where they might be coming from?

    Read the article

  • Blog: Search results prefer index page over content pages.

    - by jonescb
    I have a typical blog that has recent posts on the main page, and each post's title links to a page that only shows that one article and comments and such. I was looking through some of the keywords used to get to my site and I was noticing that some of the searches would only show my main page, and not the page for the article. If users have to find the article by scrolling through the main page, it just makes it more difficult. Is there some way that I can tell search engines to rank the content page higher than my index page? Or can I do something else like not display the full text of the posts on the main page?

    Read the article

  • How to get rid of crawling errors due to the URL Encoded Slashes (%2F) problem in Apache

    - by user14198
    The Google web crawler has indexed a whole set of URLs with encoded slashes (%2F) for our site. I assume it has picked up the pages from our XML sitemap file. The problem is that the live pages will actually result in a failure because of the Url Encoded Slashes Problem in Apache. Some solutions are mentioned here We are implementing a 301 redirect scheme for all the error pages. This should make the Google bot delete the pages from the crawling errors (no more crashing pages). Does implementing the 301s require the pages to be "live"? In that case we may be forced to implement solution 1 in the article. The problem is that solution 1 will pose a security vulnerability..

    Read the article

  • disable intel gpu in ubuntu 12.04

    - by small_potato
    I am wondering if there is anything to disable the intel gpu on ubuntu 12.04. I want to be able to setup dual monitor using nvidia-settings. It seems the intel gpu is used for display as suggested by sudo lshw -c display the output is *-display description: VGA compatible controller product: NVIDIA Corporation vendor: NVIDIA Corporation physical id: 0 bus info: pci@0000:01:00.0 version: a1 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vga_controller bus_master cap_list rom configuration: driver=nvidia latency=0 resources: irq:16 memory:c0000000-c0ffffff memory:90000000-9fffffff memory:a0000000-a1ffffff ioport:4000(size=128) memory:a2000000-a207ffff *-display description: VGA compatible controller product: Haswell Integrated Graphics Controller vendor: Intel Corporation physical id: 2 bus info: pci@0000:00:02.0 version: 06 width: 64 bits clock: 33MHz capabilities: msi pm vga_controller bus_master cap_list rom configuration: driver=i915 latency=0 resources: irq:47 memory:c2000000-c23fffff memory:b0000000-bfffffff ioport:5000(size=64) I have a lenovoY410 with GT750M. It seems there is no way to turn off the intel gpu in bios either. Help please. Thanks.

    Read the article

  • Big delay to open web pages on Ubuntu 11.10; also slow torrent client speed

    - by user54234
    The keywords for my issue are too common among other issues, so, I couldn't find anything that could answer me: why will it take around 30+ seconds for any of my browsers to open a page? happens even with google.com... with both Firefox and Chromium. This does not happen while I use Windows, from exactly the same point at my house (I've got enough wi-fi signal here for sure). Also, the standard torrent client won't hit the max download speed... I can hit 1 Mb/s with utorrent on Windows, and can't go over 300 kbps here. I tried changing the program settings, no results. Please help me. I REALLY don't wanna go back to Windows. Thanks in advance, I admire this community, and I'm sorry that I couldn't find something that could help me. I already solved a lot of issues without asking, but couldn't do it this time.

    Read the article

  • Best way to reuse common functions between ASPX pages ?

    - by DFord
    I have a bunch of functions that are used across multiple ASPX files. I want to condense these down to one file to be used for all the ASPX files. I have a few ideas but I want to know what the accepted method to doing this would be. I have an idea to just create a class to put them in. However, I was wondering if i could put them in a ascx page, but that does not look like the solution I'm looking for. Is there a accepted method for this type of situation?

    Read the article

  • multiple languages same pages shall I change the page URL path as well?

    - by Athanatos
    We own multiple country code top-level domains for our website e.g DE, UK ,FR. When someone visits for one of those domains they redirect to .com and the language automatically changes for the first time to the one from the originating domain. Also users can change the language from the .com website using a dropdown, however the page URI stays exactly the same e.g service.php. How will that be indexed in Google ? Will all the different language will be indexed or only the default lang (English) ? Is it recommended for SEO purposes to do something with the page URL (even using the htaccess maybe) so that I can also append to the title or page name the language ? e.g service.php?lang=fr

    Read the article

  • better site analytics service / script: real time statistics and time spent on pages?

    - by toPeerOrNotToPeer
    I'm looking for a site analytics software (service or script) that must be easy to comprehend. GA is simply too much complicated and it misses some key features (for me). Missing features are: real time statistics (very important) time spent on page (very important) about the "time spent on page"... i do really need a statistics software that does not calculate the time between two page views. this is not useful at all in my case. because i mostly do 1 pageview = 1 user but something that logs, for example, every 10 seconds spent on a page thank you in advance

    Read the article

  • AS3 - Unloaded AVM1 swfs trace out as unloaded but memory is not freed for the AVM2 machine

    - by puppbits
    I have a large project built in as3. Part of its main functionality is to load and unload various as2 swfs. The problem is that the memory ins't free up once they are unloaded. I have access to the as2 swfs code base and destroyed all objects, stopped and killed timers, listeners, removed from stage, destroyed all the MovieClip.protoypes that were created. They look to be clean as far as the AS2 debugger show no remnants of the object after the destroy function is run. In AS3 i've closed the local connection, cleaned all references/listeners to the AVM1Movie and ran Loader.unloadAndStop(). The trace out in flex says the swf was unloaded but looking at windows task manager the memory usage never drops to when it was before the as2 swf was loaded. Each as2 swf can take up to 80 megs each time it's run so memory gets eaten up fast and loading and unloading a few as2 files. At this point if the AS2 swfs are unloaded the only thing that I can assume that could be left is MovieClip.prototype and/or _global, _root variables add during the AS2's run time. But i've gone through those and can't find anything else that might be sticking. Has anyone ever seen problems before with the AVM1 machine not freeing up its memory?

    Read the article

  • Does Ctypes Structures and POINTERS automatically free the memory when the Python object is deleted?

    - by jsbueno
    When using Python CTypes there are the Structures, that allow you to clone c-structures on the Python side, and the POINTERS objects that create a sofisticated Python Object from a memory address value and can be used to pass objects by reference back and forth C code. What I could not find on the documentation or elsewhere is what happens when a Python object containing a Structure class that was de-referenced from a returning pointer from C Code (that is - the C function alocated memory for the structure) is itself deleted. Is the memory for the original C structure freed? If not how to do it? Furthermore -- what if the Structure contains Pointers itself, to other data that was also allocated by the C function? Does the deletion of the Structure object frees the Pointers onits members? (I doubt so) Else - -how to do it? Trying to call the system "free" from Python for the Pointers in the Structure is crashing Python for me. In other words, I have this structure filled up by a c Function call: class PIX(ctypes.Structure): """Comments not generated """ _fields_ = [ ("w", ctypes.c_uint32), ("h", ctypes.c_uint32), ("d", ctypes.c_uint32), ("wpl", ctypes.c_uint32), ("refcount", ctypes.c_uint32), ("xres", ctypes.c_uint32), ("yres", ctypes.c_uint32), ("informat", ctypes.c_int32), ("text", ctypes.POINTER(ctypes.c_char)), ("colormap", ctypes.POINTER(PIXCOLORMAP)), ("data", ctypes.POINTER(ctypes.c_uint32)) ] And I want to free the memory it is using up from Python code.

    Read the article

  • how can I save/keep-in-sync an in-memory graph of objects with the database?

    - by Greg
    Question - What is a good best practice approach for how can I save/keep-in-sync an jn-memory graph of objects with the database? Background: That is say I have the classes Node and Relationship, and the application is building up a graph of related objects using these classes. There might be 1000 nodes with various relationships between them. The application needs to query the structure hence an in-memory approach is good for performance no doubt (e.g. traverse the graph from Node X to find the root parents) The graph does need to be persisted however into a database with tables NODES and RELATIONSHIPS. Therefore what is a good best practice approach for how can I save/keep-in-sync an jn-memory graph of objects with the database? Ideal requirements would include: build up changes in-memory and then 'save' afterwards (mandatory) when saving, apply updates to database in correct order to avoid hitting any database constraints (mandatory) keep persistence mechanism separate from model, for ease in changing persistence layer if needed, e.g. don't just wrap an ADO.net DataRow in the Node and Relationship classes (desirable) mechanism for doing optimistic locking (desirable) Or is the overhead of all this for a smallish application just not worth it and I should just hit the database each time for everything? (assuming the response times were acceptable) [would still like to avoid if not too much extra overhead to remain somewhat scalable re performance]

    Read the article

  • Correct way to switch between UIView with ARC. My way leads to memory leaks :( (iOS)

    - by Andrei Golubev
    i use xcode 4.4 with ARC on.. I have dynamically created UIViews in the ViewController.m: UIView*myviews[10]; Then in the - (void)viewDidLoad function i fill each of it with pictures i need myviews[viewIndex] = [[UIView alloc]initWithFrame:myrec]; UIImage *testImg; UIImageView * testImgView; testImg = [UIImage imageNamed:[NSString stringWithFormat:@"imgarray%d.png", viewIndex]; testImgView.image = testImg; viewindex++; So all seems to be fine, when i want to jump from one view to another i do with two buttons next: [self.view addSubview:views[viewIndex]]; CATransition *animation = [CATransition animation]; [animation setDelegate:self]; [animation setDuration:1.0f]; [animation setType:@"rippleEffect"]; [animation setSubtype:kCATransitionFromTop]; //[animation setTimingFunction:[CAMediaTimingFunction functionWithName:kCAMediaTimingFunctionEaseInEaseOut]]; [self.view.layer addAnimation:animation forKey:@"transitionViewAnimation"]; Nothing seems to be bad, but the memory consumption grows with huge speed when i switch between views.. and then i get low memory warning or sometimes application will just crash. I have tried to use UIViewController array and was switching between the controllers: nothing changes, the memory low warning is what i end up with.. Maybe i need to clean the memory somehow? But how? ARC does not allow to use release and so on.. last what i have tried (sorry, maybe not very professional) before to add new subview is this NSArray *viewsToRemove = [self.view subviews]; for (UIView *views in viewsToRemove) { [views removeFromSuperview]; } But this does not help either.. Please don't judge too strong, i am still new to iOS and Objective-c..

    Read the article

  • Good C++ array class for dealing with large arrays of data in a fast and memory efficient way?

    - by Shane MacLaughlin
    Following on from a previous question relating to heap usage restrictions, I'm looking for a good standard C++ class for dealing with big arrays of data in a way that is both memory efficient and speed efficient. I had been allocating the array using a single malloc/HealAlloc but after multiple trys using various calls, keep falling foul of heap fragmentation. So the conclusion I've come to, other than porting to 64 bit, is to use a mechanism that allows me to have a large array spanning multiple smaller memory fragments. I don't want an alloc per element as that is very memory inefficient, so the plan is to write a class that overrides the [] operator and select an appropriate element based on the index. Is there already a decent class out there to do this, or am I better off rolling my own? From my understanding, and some googling, a 32 bit Windows process should theoretically be able address up to 2GB. Now assuming I've 2GB installed, and various other processes and services are hogging about 400MB, how much usable memory do you think my program can reasonably expect to get from the heap? I'm currently using various flavours of Visual C++.

    Read the article

  • java threads don't see shared boolean changes

    - by andymur
    Here the code class Aux implements Runnable { private Boolean isOn = false; private String statusMessage; private final Object lock; public Aux(String message, Object lock) { this.lock = lock; this.statusMessage = message; } @Override public void run() { for (;;) { synchronized (lock) { if (isOn && "left".equals(this.statusMessage)) { isOn = false; System.out.println(statusMessage); } else if (!isOn && "right".equals(this.statusMessage)) { isOn = true; System.out.println(statusMessage); } if ("left".equals(this.statusMessage)) { System.out.println("left " + isOn); } } } } } public class Question { public static void main(String [] args) { Object lock = new Object(); new Thread(new Aux("left", lock)).start(); new Thread(new Aux("right", lock)).start(); } } In this code I expect to see: left, right, left right and so on, but when Thread with "left" message changes isOn to false, Thread with "right" message don't see it and I get ("right true" and "left false" console messages), left thread don't get isOn in true, but right Thread can't change it cause it always see old isOn value (true). When i add volatile modifier to isOn nothing changes, but if I change isOn to some class with boolean field and change this field then threads are see changes and it works fine Thanks in advance.

    Read the article

  • Problem Initializing an Array Of Structs

    - by FallSe7en
    I am trying to initialize the following array of the following struct, but my code isn't compiling. Can anybody help me out? The struct/array: struct DiningCarSeat { int status; int order; int waiterNum; Lock customerLock; Condition customer; DiningCarSeat(seatNum) { char* tempLockName; sprintf(tempLockName, "diningCarSeatLock%d", seatNum); char* tempConditionName; sprintf(tempConditionName, "diningCarSeatCondition%d", seatNum); status = 0; order = 0; waiterNum = -1; customerLock = new Lock(tempLockName); customer = new Condition(tempConditionName); } } diningCarSeat[DINING_CAR_CAPACITY]; The relevant errors: ../threads/threadtest.cc: In constructor `DiningCarSeat::DiningCarSeat(int)': ../threads/threadtest.cc:58: error: no matching function for call to `Lock::Lock()' ../threads/synch.h:66: note: candidates are: Lock::Lock(const Lock&) ../threads/synch.h:68: note: Lock::Lock(char*) ../threads/threadtest.cc:58: error: no matching function for call to `Condition::Condition()' ../threads/synch.h:119: note: candidates are: Condition::Condition(const Condition&) ../threads/synch.h:121: note: Condition::Condition(char*) ../threads/threadtest.cc:63: error: expected primary-expression before '.' token ../threads/threadtest.cc:64: error: expected primary-expression before '.' token ../threads/threadtest.cc: At global scope: ../threads/threadtest.cc:69: error: no matching function for call to `DiningCarSeat::DiningCarSeat()' ../threads/threadtest.cc:51: note: candidates are: DiningCarSeat::DiningCarSeat(const DiningCarSeat&) ../threads/threadtest.cc:58: note: DiningCarSeat::DiningCarSeat(int) Thanks in advance!

    Read the article

< Previous Page | 208 209 210 211 212 213 214 215 216 217 218 219  | Next Page >