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  • Writing algorithm on 2D data set in plain english

    - by Alexandre P. Levasseur
    I have started an introductory Java class and the material is absolutely horrendous and I have to get excellent grades to be accepted into the master's degree, hence my very beginner question: In my assignment I have to write algorithms (no pseudo-code yet) to solve a board game (Sudoku). Essentially, the notes say that an algorithm is specification of the input(s), the output(s) and the treatments applied to the input to get the output. My question lies on the wording of algorithms because I could probably code it but I can't seem to put it on paper in a coherent way. The game has a 9x9 board and one of the algorithms to write has to find the solution by looking at 3 squares (either horizontal or vertical) and see if one of the three sub-squares match the number you are looking for. If none match then the number you are looking to place is in one of the other 2 set of 3 sub-squares (see image to get a better idea). I really can't get my head around how to formulate the solution into the terms described above or maybe it's just too simple, here's what I was thinking: Input: A 2-dimensional set of data of size 9 by 9 to be solved and a number to search for. Ouput: A 2-dimensional set of data of size 9 by 9 either solved or partially solved. Treatment: Scan each set of 3x9 and 9x3 squares. For each line or column of a 3x3 square check if the number matches a line (or column). If it does then move to the next line (or column). If not then proceed to the next 3x3 square in the same line (or column). Rinse and repeat. Does that make sense as an algorithm written in plain english ? I'm not looking for an answer to the algorithm per se but rather on the formulation of algorithms in plain english.

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  • Crowdsourcing MVVM Light Toolkit support

    - by Laurent Bugnion
    Considering the number of emails that are sent to me asking for support for MVVM Light toolkit, I find myself unable to answer all of them in sufficient time to make me feel good. In consequence, I started to send the following message in response to support queries, either per email or on the MVVM Light Codeplex discussion page. Hi, I am doing my best to answer all the questions as fast as possible. I receive a lot of them, however, and cannot reply to everyone fast enough to make me happy. Due to this, I would like to encourage you to post your question on StackOverflow, and tag it with the tag mvvm-light. StackOverflow is an awesome site where tons of developers help others with their technical question. http://stackoverflow.com/questions/tagged/mvvm-light I will monitor this tag on the StackOverflow website and do my best to answer questions. The advantage of StackOverflow over the Codeplex discussion is the sheer number of qualified developers able to help you with your questions, the visibility of the question itself, and the whole StackOverflow infrastructure (reputation, up- or down-vote, comments, etc) Thanks! Laurent Bug reports Regarding bug reports, feel free to continue to send them to the Codeplex site (preferred), or to me directly. I hope that this will help all support queries to be answered faster, and with the great quality for which the StackOverflow users are known!   Laurent Bugnion (GalaSoft) Subscribe | Twitter | Facebook | Flickr | LinkedIn

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  • NEC uPD720200 USB 3.0 not working on Ubuntu 12.04

    - by Jagged
    I've recently installed Ubuntu 12.04 64-bit on a HP Envy 15 1104tx. Most stuff appears to be working fine with the exception of the two USB3 ports (USB2 port works fine). I've read a lot of articles but so far have not been able to find a solution. I've tried adding 'pci=nomsi' to '/etc/default/grub' but this made no difference. Some articles suggest booting into Windows and upgrading the firmware on the uPD720200. Any body had any experience of this? Is there a way I can checked the firmware version of the NEC uPD720200 in Linux to see if there is an update available? Any help appreciated. uname -a: Linux HP-ENVY-15-1104tx 3.2.0-26-generic #41-Ubuntu SMP Thu Jun 14 17:49:24 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux lshw: hp-envy-15-1104tx description: Notebook product: HP ENVY 15 Notebook PC (WF591PA#ABG) vendor: Hewlett-Packard version: 0492110000241910001420000 serial: CNF0301C79 width: 64 bits capabilities: smbios-2.6 dmi-2.6 vsyscall32 configuration: boot=normal chassis=notebook family=103C_5335KV sku=WF591PA#ABG uuid=434E4630-3330-3143-3739-60EB6906688F *-core description: Motherboard product: 1522 vendor: Hewlett-Packard physical id: 0 version: 36.35 serial: CNF0301C79 slot: Base Board Chassis Location *-firmware description: BIOS vendor: Hewlett-Packard physical id: 0 version: F.2B date: 10/12/2010 size: 1MiB capacity: 1472KiB capabilities: pci upgrade shadowing cdboot bootselect edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb biosbootspecification *-memory description: System Memory physical id: 13 slot: System board or motherboard size: 16GiB *-bank:0 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 0 serial: E13C4316 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 1 serial: E03C3E16 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:2 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 2 serial: 672279CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:3 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 3 serial: 652286CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-cpu description: CPU product: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz vendor: Intel Corp. physical id: 1d bus info: cpu@0 version: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz slot: CPU size: 1199MHz capacity: 1199MHz width: 64 bits clock: 1066MHz capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 popcnt lahf_lm ida tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: cores=4 enabledcores=4 threads=8 *-cache:0 description: L3 cache physical id: 1e slot: L3 Cache size: 8MiB capacity: 8MiB capabilities: synchronous internal write-through unified *-cache:1 description: L2 cache physical id: 20 slot: L2 Cache size: 256KiB capacity: 256KiB capabilities: synchronous internal write-through unified *-cache:2 description: L1 cache physical id: 21 slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through instruction *-cache description: L1 cache physical id: 1f slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through data *-pci:0 description: Host bridge product: Core Processor DMI vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 11 width: 32 bits clock: 33MHz *-pci:0 description: PCI bridge product: Core Processor PCI Express Root Port 1 vendor: Intel Corporation physical id: 3 bus info: pci@0000:00:03.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:4000(size=4096) memory:d4100000-d41fffff ioport:c0000000(size=268435456) *-display description: VGA compatible controller product: Broadway PRO [Mobility Radeon HD 5800 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0 bus info: pci@0000:01:00.0 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi vga_controller bus_master cap_list rom configuration: driver=fglrx_pci latency=0 resources: irq:58 memory:c0000000-cfffffff memory:d4100000-d411ffff ioport:4000(size=256) memory:d4140000-d415ffff *-multimedia description: Audio device product: Juniper HDMI Audio [Radeon HD 5700 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0.1 bus info: pci@0000:01:00.1 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:56 memory:d4120000-d4123fff *-pci:1 description: PCI bridge product: Core Processor PCI Express Root Port 3 vendor: Intel Corporation physical id: 5 bus info: pci@0000:00:05.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 memory:d4000000-d40fffff *-usb description: USB controller product: uPD720200 USB 3.0 Host Controller vendor: NEC Corporation physical id: 0 bus info: pci@0000:02:00.0 version: 03 width: 64 bits clock: 33MHz capabilities: pm msi msix pciexpress xhci bus_master cap_list configuration: driver=xhci_hcd latency=0 resources: irq:16 memory:d4000000-d4001fff *-generic:0 UNCLAIMED description: System peripheral product: Core Processor System Management Registers vendor: Intel Corporation physical id: 8 bus info: pci@0000:00:08.0 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:1 UNCLAIMED description: System peripheral product: Core Processor Semaphore and Scratchpad Registers vendor: Intel Corporation physical id: 8.1 bus info: pci@0000:00:08.1 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:2 UNCLAIMED description: System peripheral product: Core Processor System Control and Status Registers vendor: Intel Corporation physical id: 8.2 bus info: pci@0000:00:08.2 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:3 UNCLAIMED description: System peripheral product: Core Processor Miscellaneous Registers vendor: Intel Corporation physical id: 8.3 bus info: pci@0000:00:08.3 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:4 UNCLAIMED description: System peripheral product: Core Processor QPI Link vendor: Intel Corporation physical id: 10 bus info: pci@0000:00:10.0 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:5 UNCLAIMED description: System peripheral product: Core Processor QPI Routing and Protocol Registers vendor: Intel Corporation physical id: 10.1 bus info: pci@0000:00:10.1 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-multimedia description: Audio device product: 5 Series/3400 Series Chipset High Definition Audio vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 05 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:55 memory:d4200000-d4203fff *-pci:2 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:17 ioport:3000(size=4096) memory:d3000000-d3ffffff ioport:d0000000(size=16777216) *-network description: Wireless interface product: Centrino Advanced-N 6200 vendor: Intel Corporation physical id: 0 bus info: pci@0000:03:00.0 logical name: wlan0 version: 35 serial: 00:27:10:40:e4:68 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=iwlwifi driverversion=3.2.0-26-generic firmware=9.221.4.1 build 25532 latency=0 link=no multicast=yes wireless=IEEE 802.11abgn resources: irq:54 memory:d3000000-d3001fff *-pci:3 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:2000(size=4096) memory:d2000000-d2ffffff ioport:d1000000(size=16777216) *-network description: Ethernet interface product: AR8131 Gigabit Ethernet vendor: Atheros Communications Inc. physical id: 0 bus info: pci@0000:04:00.0 logical name: eth0 version: c0 serial: 60:eb:69:06:68:8f size: 1Gbit/s capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vpd bus_master cap_list ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=atl1c driverversion=1.0.1.0-NAPI duplex=full firmware=N/A ip=10.161.0.147 latency=0 link=yes multicast=yes port=twisted pair speed=1Gbit/s resources: irq:57 memory:d2000000-d203ffff ioport:2000(size=128) *-usb description: USB controller product: 5 Series/3400 Series Chipset USB2 Enhanced Host Controller vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 05 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:20 memory:d4205800-d4205bff *-pci:4 description: PCI bridge product: 82801 Mobile PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci@0000:00:1e.0 version: a5 width: 32 bits clock: 33MHz capabilities: pci subtractive_decode bus_master cap_list *-isa description: ISA bridge product: Mobile 5 Series Chipset LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 05 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: RAID bus controller product: 82801 Mobile SATA Controller [RAID mode] vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 version: 05 width: 32 bits clock: 66MHz capabilities: storage msi pm bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:45 ioport:5048(size=8) ioport:5054(size=4) ioport:5040(size=8) ioport:5050(size=4) ioport:5020(size=32) memory:d4205000-d42057ff *-disk description: ATA Disk product: OCZ-VERTEX3 physical id: 0.0.0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 2.15 serial: OCZ-0350P6H316X5KUQE size: 223GiB (240GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=000592dd *-volume:0 description: EXT4 volume vendor: Linux physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 logical name: / version: 1.0 serial: e741f18c-cfc5-4bce-b1e7-f80e517a3a22 size: 207GiB capacity: 207GiB capabilities: primary bootable journaled extended_attributes large_files huge_files dir_nlink recover extents ext4 ext2 initialized configuration: created=2012-06-15 06:49:27 filesystem=ext4 lastmountpoint=/ modified=2012-06-14 21:23:42 mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,user_xattr,barrier=1,data=ordered mounted=2012-07-10 16:18:20 state=mounted *-volume:1 description: Extended partition physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 size: 15GiB capacity: 15GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 15GiB capabilities: nofs *-serial UNCLAIMED description: SMBus product: 5 Series/3400 Series Chipset SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 05 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:d4205c00-d4205cff ioport:5000(size=32) *-pci:1 description: Host bridge product: Core Processor QuickPath Architecture Generic Non-Core Registers vendor: Intel Corporation physical id: 101 bus info: pci@0000:ff:00.0 version: 04 width: 32 bits clock: 33MHz *-pci:2 description: Host bridge product: Core Processor QuickPath Architecture System Address Decoder vendor: Intel Corporation physical id: 102 bus info: pci@0000:ff:00.1 version: 04 width: 32 bits clock: 33MHz *-pci:3 description: Host bridge product: Core Processor QPI Link 0 vendor: Intel Corporation physical id: 103 bus info: pci@0000:ff:02.0 version: 04 width: 32 bits clock: 33MHz *-pci:4 description: Host bridge product: Core Processor QPI Physical 0 vendor: Intel Corporation physical id: 104 bus info: pci@0000:ff:02.1 version: 04 width: 32 bits clock: 33MHz *-pci:5 description: Host bridge product: Core Processor Integrated Memory Controller vendor: Intel Corporation physical id: 105 bus info: pci@0000:ff:03.0 version: 04 width: 32 bits clock: 33MHz *-pci:6 description: Host bridge product: Core Processor Integrated Memory Controller Target Address Decoder vendor: Intel Corporation physical id: 106 bus info: pci@0000:ff:03.1 version: 04 width: 32 bits clock: 33MHz *-pci:7 description: Host bridge product: Core Processor Integrated Memory Controller Test Registers vendor: Intel Corporation physical id: 107 bus info: pci@0000:ff:03.4 version: 04 width: 32 bits clock: 33MHz *-pci:8 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Control Registers vendor: Intel Corporation physical id: 108 bus info: pci@0000:ff:04.0 version: 04 width: 32 bits clock: 33MHz *-pci:9 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Address Registers vendor: Intel Corporation physical id: 109 bus info: pci@0000:ff:04.1 version: 04 width: 32 bits clock: 33MHz *-pci:10 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Rank Registers vendor: Intel Corporation physical id: 10a bus info: pci@0000:ff:04.2 version: 04 width: 32 bits clock: 33MHz *-pci:11 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Thermal Control Registers vendor: Intel Corporation physical id: 10b bus info: pci@0000:ff:04.3 version: 04 width: 32 bits clock: 33MHz *-pci:12 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Control Registers vendor: Intel Corporation physical id: 10c bus info: pci@0000:ff:05.0 version: 04 width: 32 bits clock: 33MHz *-pci:13 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Address Registers vendor: Intel Corporation physical id: 10d bus info: pci@0000:ff:05.1 version: 04 width: 32 bits clock: 33MHz *-pci:14 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Rank Registers vendor: Intel Corporation physical id: 10e bus info: pci@0000:ff:05.2 version: 04 width: 32 bits clock: 33MHz *-pci:15 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Thermal Control Registers vendor: Intel Corporation physical id: 10f bus info: pci@0000:ff:05.3 version: 04 width: 32 bits clock: 33MHz *-battery description: Lithium Ion Battery product: NK06053 vendor: SMP-ATL24 physical id: 1 slot: Primary capacity: 4800mWh configuration: voltage=11.1V lspci: 02:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) (prog-if 30 [XHCI]) Subsystem: Hewlett-Packard Company Device 1522 Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at d4000000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150] Latency Tolerance Reporting Kernel driver in use: xhci_hcd lsusb (with thumb drive plugged into USB3 port): Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 003 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 001 Device 002: ID 8087:0020 Intel Corp. Integrated Rate Matching Hub Bus 001 Device 003: ID 5986:01d0 Acer, Inc Bus 001 Device 004: ID 03f0:231d Hewlett-Packard

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  • IASA South East Florida Chapter Meeting Recap - June 2011

    - by Sam Abraham
    Erik Russell and Giles Marino were our speakers for the June 2011 IASA South East Florida Chapter meeting.    Attendees filled all available seats at the Microsoft office conference room where the event was held. This highlights the high interest in Enterprise Architecture as a career track and chartered project role. Also in attendance were our Board of Directors and Alex Funkhouser, President, Sherlock Technology.   Rainer Habermann, Chapter President, kicked off the meeting by introducing our speakers and Board of Directors.   Alex Funkhouser, President of South Florida’s staffing firm Sherlock Technology spoke briefly about available Software Architect positions in the area. Alex also congratulated and presented this week’s Sherlock Raffle winner with $500 in cash.   Our speakers Giles and Erik then proceeded with their talk. Erik presented a business case in the government sector where Enterprise Architecture helped a government entity cut costs and streamline its various business operations. Technologies leveraged in Erik’s demonstrated project were Java-based.   Giles then followed with a thorough demonstration of the Architecture patterns he used to migrate a complete backend system for an insurance company to the .Net Platform.   Audience was very engaged with our speakers as evidenced by the large number of follow-up questions asked at the end of the talk.   We greatly enjoyed Giles and Erik’s talk and look forward to having them share with us more of their adventures as Enterprise Architects in the near future.   Below are some photos of the event.   Sam Abraham Secretary- IASA South East Florida Chapter. http://www.iasaglobal.org/iasa/South_East_Florida.asp Chapter President - Rainer Habermann kicks off our meeting.   Sherlock Technology President Alex Funkhouser holding Sherlock's weekly cash prize. Alex shares available Software Architect opportunities with our members Erik Russell addressing our membership Giles Marino sharing his architecture experience in the insurance industry In this photo: Dave Noderer, Rainer Habermann, Quent Herschelman and Alex Funkhouser. Event attracted a large audience and filled the Microsoft conference room where it was held

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  • UK Connected Systems User Group Recap from July

    - by Michael Stephenson
    Originally posted on: http://geekswithblogs.net/michaelstephenson/archive/2013/07/29/153557.aspxJust a note to recap some of the discussion and activity from the recent UK Connected Systems User Group in July.AppFx.ServiceBusWe discussed some of the implementation details of the AppFx.ServiceBus codeplex project.  This brought up some discussion around peoples experiences with Windows Azure Service Bus and how this codeplex project can help.  The slides from this presentation are available at the following location.https://appfxservicebus.codeplex.com/downloads/get/711481BizTalk Maturity AssessmentThe session around the BizTalk Maturity Assessment brought up some interesting discussions.  I have created a video about the content from this session which is available online.To findout more about the BizTalk Maturity Assessment refer to:http://www.biztalkmaturity.com/To view the video refer to:http://www.youtube.com/watch?v=MZ1eC5SCDogOther NewsHybrid Organisation EventThe next user group session will be a full day event on the 11th September called The Hybrid Organisation.  We have some great sessions lined up and you can findout more about this event on the following link:http://ukcsug-hybridintegration-sept2013.eventbrite.com/Saravana's BizTalk Services VideosSaravana has recently published some BizTalk Services videos that he wanted to share with everyone.http://blogs.biztalk360.com/windows-azure-biztalk-serviceshello-word-and-hybrid-scenarios-demo-videos/Hope to see everyone soon and let me know if anyone has any questionsRegardsMike

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  • 30 in 60 Contest | Standings Update

    - by Staff of Geeks
    The contest has definitely ended the first week with a clear leader.  One of our new bloggers, Enrique Lima, has posted 20 times since the beginning of the contest with some great content on Team Foundation Server.  Another noticeable face we see on the leader board is Chris Williams who is making headway.  Chris, are you going to challenge up D’Arcy Lussier for the lead position on GWB again, notice who isn’t on this list :D.  Also, Chris House who is a new blogger is making some strong strides.  And finally, let us not forget Dave Campbell who writes Silverlight Cream who always has great content for us.  We hope to see more names joining this list soon, what else could be better than a world full of Geekswithblogs.net custom shirts?   Current Leader Board: Enrique Lima (20 posts) - http://geekswithblogs.net/enriquelima Eric Nelson (7 posts) - http://geekswithblogs.net/iupdateable Christopher House (7 posts) - http://geekswithblogs.net/13DaysaWeek StuartBrierley (7 posts) - http://geekswithblogs.net/StuartBrierley Dave Campbell (6 posts) - http://geekswithblogs.net/WynApseTechnicalMusings Chris Williams (5 posts) - http://geekswithblogs.net/cwilliams Frez (4 posts) - http://geekswithblogs.net/Frez MarkPearl (4 posts) - http://geekswithblogs.net/MarkPearl mbcrump (4 posts) - http://geekswithblogs.net/mbcrump Rajesh Charagandla (3 posts) - http://geekswithblogs.net/crajesh Technorati Tags: 30 in 60,Geekswithblogs,Standings

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  • Professional Scrum Developer (.NET) Training in London

    - by Martin Hinshelwood
    On the 26th - 30th July in Microsoft’s offices in London Adam Cogan from SSW will be presenting the first Professional Scrum Developer course in the UK. I will be teaching this course along side Adam and it is a fantastic experience. You are split into teams and go head-to-head to deliver units of potentially shippable work in four two hour sprints. The Professional Scrum Developer course is the only course endorsed by both Microsoft and Ken Schwaber and they have worked together very effectively in brining this course to fruition. This course is the brain child of Richard Hundhausen, a Microsoft Regional Director, and both Adam and I attending the Trainer Prep in Sydney when he was there earlier this year. He is a fantastic trainer and no matter where you do this course you can be safe in the knowledge that he has trained and vetted all of the teachers. A tools version of Ken if you will Find a course and register Download this syllabus Download the Scrum Guide What is the Professional Scrum Developer course all about? Professional Scrum Developer course is a unique and intensive five-day experience for software developers. The course guides teams on how to turn product requirements into potentially shippable increments of software using the Scrum framework, Visual Studio 2010, and modern software engineering practices. Attendees will work in self-organizing, self-managing teams using a common instance of Team Foundation Server 2010. Who should attend this course? This course is suitable for any member of a software development team – architect, programmer, database developer, tester, etc. Entire teams are encouraged to attend and experience the course together, but individuals are welcome too. Attendees will self-organize to form cross-functional Scrum teams. These teams require an aggregate of skills specific to the selected case study. Please see the last page of this document for specific details. Product Owners, ScrumMasters, and other stakeholders are welcome too, but keep in mind that everyone who attends will be expected to commit to work and pull their weight on a Scrum team. What should you know by the end of the course? Scrum will be experienced through a combination of lecture, demonstration, discussion, and hands-on exercises. Attendees will learn how to do Scrum correctly while being coached and critiqued by the instructor, in the following topic areas: Form effective teams Explore and understand legacy “Brownfield” architecture Define quality attributes, acceptance criteria, and “done” Create automated builds How to handle software hotfixes Verify that bugs are identified and eliminated Plan releases and sprints Estimate product backlog items Create and manage a sprint backlog Hold an effective sprint review Improve your process by using retrospectives Use emergent architecture to avoid technical debt Use Test Driven Development as a design tool Setup and leverage continuous integration Use Test Impact Analysis to decrease testing times Manage SQL Server development in an Agile way Use .NET and T-SQL refactoring effectively Build, deploy, and test SQL Server databases Create and manage test plans and cases Create, run, record, and play back manual tests Setup a branching strategy and branch code Write more maintainable code Identify and eliminate people and process dysfunctions Inspect and improve your team’s software development process What does the week look like? This course is a mix of lecture, demonstration, group discussion, simulation, and hands-on software development. The bulk of the course will be spent working as a team on a case study application delivering increments of new functionality in mini-sprints. Here is the week at a glance: Monday morning and most of the day Friday will be spent with the computers powered off, so you can focus on sharpening your game of Scrum and avoiding the common pitfalls when implementing it. The Sprints Timeboxing is a critical concept in Scrum as well as in this course. We expect each team and student to understand and obey all of the timeboxes. The timebox duration will always be clearly displayed during each activity. Expect the instructor to enforce it. Each of the ½ day sprints will roughly follow this schedule: Component Description Minutes Instruction Presentation and demonstration of new and relevant tools & practices 60 Sprint planning meeting Product owner presents backlog; each team commits to delivering functionality 10 Sprint planning meeting Each team determines how to build the functionality 10 The Sprint The team self-organizes and self-manages to complete their tasks 120 Sprint Review meeting Each team will present their increment of functionality to the other teams = 30 Sprint Retrospective A group retrospective meeting will be held to inspect and adapt 10 Each team is expected to self-organize and manage their own work during the sprint. Pairing is highly encouraged. The instructor/product owner will be available if there are questions or impediments, but will be hands-off by default. You should be prepared to communicate and work with your team members in order to achieve your sprint goal. If you have development-related questions or get stuck, your partner or team should be your first level of support. Module 1: INTRODUCTION This module provides a chance for the attendees to get to know the instructors as well as each other. The Professional Scrum Developer program, as well as the day by day agenda, will be explained. Finally, the Scrum team will be selected and assembled so that the forming, storming, norming, and performing can begin. Trainer and student introductions Professional Scrum Developer program Agenda Logistics Team formation Retrospective Module 2: SCRUMDAMENTALS This module provides a level-setting understanding of the Scrum framework including the roles, timeboxes, and artifacts. The team will then experience Scrum firsthand by simulating a multi-day sprint of product development, including planning, review, and retrospective meetings. Scrum overview Scrum roles Scrum timeboxes (ceremonies) Scrum artifacts Simulation Retrospective It’s required that you read Ken Schwaber’s Scrum Guide in preparation for this module and course. MODULE 3: IMPLEMENTING SCRUM IN VISUAL STUDIO 2010 This module demonstrates how to implement Scrum in Visual Studio 2010 using a Scrum process template*. The team will learn the mapping between the Scrum concepts and how they are implemented in the tool. After connecting to the shared Team Foundation Server, the team members will then return to the simulation – this time using Visual Studio to manage their product development. Mapping Scrum to Visual Studio 2010 User Story work items Task work items Bug work items Demonstration Simulation Retrospective Module 4: THE CASE STUDY In this module the team is introduced to their problem domain for the week. A kickoff meeting by the Product Owner (the instructor) will set the stage for the why and what that will take during the upcoming sprints. The team will then define the quality attributes of the project and their definition of “done.” The legacy application code will be downloaded, built, and explored, so that any bugs can be discovered and reported. Introduction to the case study Download the source code, build, and explore the application Define the quality attributes for the project Define “done” How to file effective bugs in Visual Studio 2010 Retrospective Module 5: HOTFIX This module drops the team directly into a Brownfield (legacy) experience by forcing them to analyze the existing application’s architecture and code in order to locate and fix the Product Owner’s high-priority bug(s). The team will learn best practices around finding, testing, fixing, validating, and closing a bug. How to use Architecture Explorer to visualize and explore Create a unit test to validate the existence of a bug Find and fix the bug Validate and close the bug Retrospective Module 6: PLANNING This short module introduces the team to release and sprint planning within Visual Studio 2010. The team will define and capture their goals as well as other important planning information. Release vs. Sprint planning Release planning and the Product Backlog Product Backlog prioritization Acceptance criteria and tests Sprint planning and the Sprint Backlog Creating and linking Sprint tasks Retrospective At this point the team will have the knowledge of Scrum, Visual Studio 2010, and the case study application to begin developing increments of potentially shippable functionality that meet their definition of done. Module 7: EMERGENT ARCHITECTURE This module introduces the architectural practices and tools a team can use to develop a valid design on which to develop new functionality. The teams will learn how Scrum supports good architecture and design practices. After the discussion, the teams will be presented with the product owner’s prioritized backlog so that they may select and commit to the functionality they can deliver in this sprint. Architecture and Scrum Emergent architecture Principles, patterns, and practices Visual Studio 2010 modeling tools UML and layer diagrams SPRINT 1 Retrospective Module 8: TEST DRIVEN DEVELOPMENT This module introduces Test Driven Development as a design tool and how to implement it using Visual Studio 2010. To maximize productivity and quality, a Scrum team should setup Continuous Integration to regularly build every team member’s code changes and run regression tests. Refactoring will also be defined and demonstrated in combination with Visual Studio’s Test Impact Analysis to efficiently re-run just those tests which were impacted by refactoring. Continuous integration Team Foundation Build Test Driven Development (TDD) Refactoring Test Impact Analysis SPRINT 2 Retrospective Module 9: AGILE DATABASE DEVELOPMENT This module lets the SQL Server database developers in on a little secret – they can be agile too. By using the database projects in Visual Studio 2010, the database developers can join the rest of the team. The students will see how to apply Agile database techniques within Visual Studio to support the SQL Server 2005/2008/2008R2 development lifecycle. Agile database development Visual Studio database projects Importing schema and scripts Building and deploying Generating data Unit testing SPRINT 3 Retrospective Module 10: SHIP IT Teams need to know that just because they like the functionality doesn’t mean the Product Owner will. This module revisits acceptance criteria as it pertains to acceptance testing. By refining acceptance criteria into manual test steps, team members can execute the tests, recording the results and reporting bugs in a number of ways. Manual tests will be defined and executed using the Microsoft Test Manager tool. As the Sprint completes and an increment of functionality is delivered, the team will also learn why and when they should create a branch of the codeline. Acceptance criteria Testing in Visual Studio 2010 Microsoft Test Manager Writing and running manual tests Branching SPRINT 4 Retrospective Module 11: OVERCOMING DYSFUNCTION This module introduces the many types of people, process, and tool dysfunctions that teams face in the real world. Many dysfunctions and scenarios will be identified, along with ideas and discussion for how a team might mitigate them. This module will enable you and your team to move toward independence and improve your game of Scrum when you depart class. Scrum-butts and flaccid Scrum Best practices working as a team Team challenges ScrumMaster challenges Product Owner challenges Stakeholder challenges Course Retrospective What will be expected of you and you team? This is a unique course in that it’s technically-focused, team-based, and employs timeboxes. It demands that the members of the teams self-organize and self-manage their own work to collaboratively develop increments of software. All attendees must commit to: Pay attention to all lectures and demonstrations Participate in team and group discussions Work collaboratively with other team members Obey the timebox for each activity Commit to work and do your best to deliver All teams should have these skills: Understanding of Scrum Familiarity with Visual Studio 201 C#, .NET 4.0 & ASP.NET 4.0 experience*  SQL Server 2008 development experience Software testing experience * Check with the instructor ahead of time for the exact technologies Self-organising teams Another unique attribute of this course is that it’s a technical training class being delivered to teams of developers, not pairs, and not individuals. Ideally, your actual software development team will attend the training to ensure that all necessary skills are covered. However, if you wish to attend an open enrolment course alone or with just a couple of colleagues, realize that you may be placed on a team with other attendees. The instructor will do his or her best to ensure that each team is cross-functional to tackle the case study, but there are no guarantees. You may be required to try a new role, learn a new skill, or pair with somebody unfamiliar to you. This is just good Scrum! Who should NOT take this course? Because of the nature of this course, as explained above, certain types of people should probably not attend this course: Students requiring command and control style instruction – there are no prescriptive/step-by-step (think traditional Microsoft Learning) labs in this course Students who are unwilling to work within a timebox Students who are unwilling to work collaboratively on a team Students who don’t have any skill in any of the software development disciplines Students who are unable to commit fully to their team – not only will this diminish the student’s learning experience, but it will also impact their team’s learning experience Find a course and register Download this syllabus Download the Scrum Guide Technorati Tags: Scrum,SSW,Pro Scrum Dev

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  • Steve Jobs Goes On Medical. iPad 2 and iPhone 5 On Track.

    - by Gopinath
    Here is a bit of disappointing news for Apple fan boys. Steve Jobs is again going on medical leave as he wants to concentrate on his health for sometime. In an email to the employees of Apple Steve said, At my request, the board of directors has granted me a medical leave of absence so I can focus on my health..I will continue as CEO and be involved in major strategic decisions for the company.I have great confidence that Tim and the rest of the executive management team will do a terrific job executing the exciting plans we have in place for 2011   Seems to the plans for release of much anticipated iPad 2 and iPhone 5 will not be affected by Steve’s absence -as rumoured iPad 2 In April, iPhone 5 In June With New Hardware. Here is the full content of the email Steve Jobs sent to all employees: Team, At my request, the board of directors has granted me a medical leave of absence so I can focus on my health. I will continue as CEO and be involved in major strategic decisions for the company. I have asked Tim Cook to be responsible for all of Apple’s day to day operations. I have great confidence that Tim and the rest of the executive management team will do a terrific job executing the exciting plans we have in place for 2011. I love Apple so much and hope to be back as soon as I can. In the meantime, my family and I would deeply appreciate respect for our privacy. Steve This article titled,Steve Jobs Goes On Medical. iPad 2 and iPhone 5 On Track., was originally published at Tech Dreams. Grab our rss feed or fan us on Facebook to get updates from us.

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  • Steve Jobs Goes On Medical. iPad 2 and iPhone 5 On Track.

    - by Gopinath
    Here is a bit of disappointing news for Apple fan boys. Steve Jobs is again going on medical leave as he wants to concentrate on his health for sometime. In an email to the employees of Apple Steve said, At my request, the board of directors has granted me a medical leave of absence so I can focus on my health..I will continue as CEO and be involved in major strategic decisions for the company.I have great confidence that Tim and the rest of the executive management team will do a terrific job executing the exciting plans we have in place for 2011   In the mail, Steve also said that plans for the product releases scheduled in 2011 will not be affected. This means as rumoured iPad 2 In April, iPhone 5 In June With New Hardware. There is not much information on the medical complications Steve is facing now, but many are thinking  its linked to the liver transplant he had in 2009. What ever may be reason, we wish for this speedy recovery. Here is the full content of the email Steve Jobs sent to all employees: Team, At my request, the board of directors has granted me a medical leave of absence so I can focus on my health. I will continue as CEO and be involved in major strategic decisions for the company. I have asked Tim Cook to be responsible for all of Apple’s day to day operations. I have great confidence that Tim and the rest of the executive management team will do a terrific job executing the exciting plans we have in place for 2011. I love Apple so much and hope to be back as soon as I can. In the meantime, my family and I would deeply appreciate respect for our privacy. Steve This article titled,Steve Jobs Goes On Medical. iPad 2 and iPhone 5 On Track., was originally published at Tech Dreams. Grab our rss feed or fan us on Facebook to get updates from us.

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  • BPMN is dead, long live BPEL!

    - by JuergenKress
    “BPMN is dead, long live BPEL” was the title of our panel discussion during the SOA & BPM Integration Days 2011. At the JAXenter my discussion summery was just published (in German). If you want to learn more about SOA & BPM make sure you register for our up-coming conference October 12th & 13th 2011 in Düsseldorf. The speakers include the top SOA and BPM experts in Germany: Thilo Frotscher & Kornelius Fuhrer & Björn Hardegen & Nicolai Josuttis & Michael Kopp & Dr. Dirk Krafzig & Jürgen Kress & Frank Leymann & Berthold Maier & Hajo Normann & Max J. Pucher & Bernd Rücker & Dr. Gregor Scheithauer & Danilo Schmiedel & Guido Schmutz & Dirk Slama & Heiko Spindler & Volker Stiehl & Bernd Trops & Clemens Utschig-Utschig & Tammo van Lessen & Dr. Hendrik Voigt & Torsten Winterberg  For details please become a member in the SOA Partner Community for registration please visit  www.oracle.com/goto/emea/soa (OPN account required) Blog Twitter LinkedIn Mix Forum Wiki Website

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  • Silverlight Cream for June 12, 2010 -- #880

    - by Dave Campbell
    In this Issue: Michael Washington, Diego Poza, Viktor Larsson, Brian Noyes, Charles Petzold, Laurent Bugnion, Anjaiah Keesari, David Anson, and Jeremy Likness. From SilverlightCream.com: My MEF Rant Read Michael Washington's discussion about MEF from someone that's got some experience, but not enough to remember the pain points... how it works, and what he'd like to see. Prism 4: What’s new and what’s next Diego Poza Why Office Hub is important for WP7 Viktor Larsson has another WP7 post up and he's talking about the Office Hub ... good description and maybe the first I've seen on the Office Hub. WCF RIA Services Part 1: Getting Started Brian Noyes has part 1 of a 10-part tutorial series on WCF RIA Services up at SilverlightShow. This first is the intro, but it's a good one. CompositionTarget.Rendering and RenderEventArgs Charles Petzold talks about CompositionTarget.Rendering and using it for calculating time span ... and it works in WPF and WP7 too... cool example from his WPF book, and all the code. Two small issues with Windows Phone 7 ApplicationBar buttons (and workaround) Laurent Bugnion has a post up from earlier this week that I missed describing problems with the WP7 ApplicationBar ... oh, and a workaround for it :) Animation in Silverlight Anjaiah Keesari has a really extensive post up on Silverlight animation, and this is an all-XAML thing... so buckle up we're going old-school :) Two fixes for my Silverlight SplitButton/MenuButton implementation - and true WPF support David Anson revisits and revises his SplitButton code based on a couple problem reports he received. Source for the button and the test project is included. Tips and Tricks for INotifyPropertyChanged Jeremy Likness is discussing INotifyPropertyChanged and describes an extension method. He does bring up a problem associated with this, so check that out. He finishes the post off with a discussion of "Observable Enumerables" Stay in the 'Light! Twitter SilverlightNews | Twitter WynApse | WynApse.com | Tagged Posts | SilverlightCream Join me @ SilverlightCream | Phoenix Silverlight User Group Technorati Tags: Silverlight    Silverlight 3    Silverlight 4    Windows Phone MIX10

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  • International Association for Software Architects (IASA) SE Florida Chapter Inaugural Meeting - 12/6/2010

    - by Sam Abraham
    On Monday 12/6/2010, Florida witnessed the inauguration of the state’s first official chapter of the International Association for Software Architects (IASA). Present were Ms. Damaris Bode, Global IASA Chapter Director and Mr. Uday Batt, President of the Indian Chapter.   Ms. Bode spoke to us about the various benefits IASA offers to its members as well as the various available education courses and certification tracks. Mr. Batt kindly shared with us his experience in establishing and growing the Indian Chapter.   Mr. Rainer Habermann, President of the IASA South East Florida Chapter outlined his vision for the upcoming year and invited all members to take an active role while Mr. Dave Noderer, the chapter’s vice president shared the history and events that took place leading to the final inauguration.   Founding chapter board members are: -Rainer Habermann, President -Dave Noderer, Vice President -Ray Almonte, Treasurer -Quent Hershleman, Director of the Board of Directors. -Sam Abraham (Me), Secretary   Chapter meetings will be taking place at the Microsoft Ft Lauderdale office. For more information on IASA please visit http://www.iasahome.org. For more information about the SE Florida Chapter please visit http://www.iasaglobal.org/iasa/South_East_Florida.asp?SnID=1049126809 Event photos can be found on Facebook: http://www.facebook.com/album.php?aid=19508&id=100001532507436#!/album.php?aid=19508&id=100001532507436   --Sam Abraham

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  • Mission critical embedded language

    - by Moe
    Maybe the question sounds a bit strange, so i'll explain a the background a little bit. Currently i'm working on a project at y university, which will be a complete on-board software for an satellite. The system is programmed in c++ on top of a real-time operating system. However, some subsystems like the attitude control system and the fault detection and a space simulation are currently only implemented in Matlab/Simulink, to prototype the algorithms efficiently. After their verification, they will be translated into c++. The complete on-board software grew very complex, and only a handful people know the whole system. Furthermore, many of the students haven't program in c++ yet and the manual memory management of c++ makes it even more difficult to write mission critical software. Of course the main system has to be implemented in c++, but i asked myself if it's maybe possible to use an embedded language to implement the subsystem which are currently written in Matlab. This embedded language should feature: static/strong typing and compiler checks to minimize runtime errors small memory usage, and relative fast runtime attitude control algorithms are mainly numerical computations, so a good numeric support would be nice maybe some sort of functional programming feature, matlab/simulink encourage you to use it too I googled a bit, but only found Lua. It looks nice, but i would not use it in mission critical software. Have you ever encountered a situation like this, or do you know any language, which could satisfies the conditions? EDIT: To clarify some things: embedded means it should be able to embed the language into the existing c++ environment. So no compiled languages like Ada or Haskell ;)

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  • Drivers for NVIDIA 520M not working in Ubuntu 12.04

    - by Don
    I am aware that this is nominally a duplicate question, however I've read the other questions and haven't been able to resolve my problem after many hours and attempts, so please don't delete it. Additionally, it seems like many answers to the other questions are specifically dependent on certain situations. My situation being different from the others I found represented, here's my question. Until last night, I had Ubuntu 12.04 installed with Wubi, and it ran ok, though slowly and with occasional hangs. So I partitioned the drive and installed 12.04 in its own partition. Now when I start it, I am stuck using 2D. I believe this is an NVIDIA bug. My NVIDIA card is a GT 520M and my machine has Optimus. Additional Drivers only displays my wireless driver. Going to System Settings Details Graphics shows Driver:Unknown, Experience:Standard. I downloaded the driver from the NVIDIA website, and ran the installer with no errors, except that the "distribution-provided pre-install script failed". After rebooting, my screen was stuck at 640X480, which was fixed by editing /etc/X11/xorg.conf However, I still was stuck in 2D, and nothing else had changed either. A thread suggested something called Bumblebee. I tried that, and when I ran optirun firefoxI got a frozen blank screen. Following another suggestion, I checked the BIOS to try and disable Optimus. I found and ran myriad other commands to try and fix the problem and nothing changed. Now I have just done a clean re-install of Ubuntu. From there, I: Installed all the updates Downloaded the NVIDIA driver Installed it Got screen stuck at 640X480, fixed in xorg.conf. To recap the problem: I can't get the NVIDIA drivers working I am stuck using 2D I'm an idiot I think if the first one is solved, the solution to the second will naturally follow. If you need me to provide any other information, I'd be happy to. From what I've seen in other threads, I think this information may help: lsmod: dh@donsMachine:~$ lsmod Module Size Used by nvidia 12353161 0 snd_hda_codec_hdmi 32474 1 snd_hda_codec_realtek 223867 1 joydev 17693 0 parport_pc 32866 0 ppdev 17113 0 rfcomm 47604 0 bnep 18281 2 bluetooth 180104 10 rfcomm,bnep snd_hda_intel 33773 3 snd_hda_codec 127706 3 snd_hda_codec_hdmi,snd_hda_codec_realtek,snd_hda_intel snd_hwdep 13668 1 snd_hda_codec snd_pcm 97188 3 snd_hda_codec_hdmi,snd_hda_intel,snd_hda_codec uvcvideo 72627 0 videodev 98259 1 uvcvideo v4l2_compat_ioctl32 17128 1 videodev snd_seq_midi 13324 0 snd_rawmidi 30748 1 snd_seq_midi snd_seq_midi_event 14899 1 snd_seq_midi snd_seq 61896 2 snd_seq_midi,snd_seq_midi_event lib80211_crypt_tkip 17390 0 wl 2568210 0 lib80211 14381 2 lib80211_crypt_tkip,wl snd_timer 29990 2 snd_pcm,snd_seq snd_seq_device 14540 3 snd_seq_midi,snd_rawmidi,snd_seq snd 78855 16 snd_hda_codec_hdmi,snd_hda_codec_realtek,snd_hda_intel,snd_hda_codec,snd_hwdep,snd_pcm,snd_rawmidi,snd_seq,snd_timer,snd_seq_device psmouse 87692 0 serio_raw 13211 0 i915 468745 2 soundcore 15091 1 snd snd_page_alloc 18529 2 snd_hda_intel,snd_pcm drm_kms_helper 46978 1 i915 drm 242038 3 i915,drm_kms_helper mei 41616 0 i2c_algo_bit 13423 1 i915 mxm_wmi 12979 0 acer_wmi 28418 0 sparse_keymap 13890 1 acer_wmi video 19596 1 i915 wmi 19256 2 mxm_wmi,acer_wmi mac_hid 13253 0 lp 17799 0 parport 46562 3 parport_pc,ppdev,lp tg3 152032 0 sdhci_pci 18826 0 sdhci 33205 1 sdhci_pci lspci -nn | grep VGA dh@donsMachine:~$ lspci -nn | grep VGA 00:02.0 VGA compatible controller [0300]: Intel Corporation 2nd Generation Core Processor Family Integrated Graphics Controller [8086:0116] (rev 09) 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation Device [10de:0df7] (rev a1) lshw dh@donsMachine:~$ sudo lshw [sudo] password for dh: donsmachine description: Notebook product: EasyNote TS44HR () vendor: Packard Bell version: V1.12 serial: LXBWZ02017134209D71601 width: 64 bits capabilities: smbios-2.7 dmi-2.7 vsyscall32 configuration: boot=normal chassis=notebook uuid=16FE576B-CA15-11E0-B096-B870F4E51243 *-core description: Motherboard product: SJV50_HR vendor: Packard Bell physical id: 0 version: Base Board Version serial: Base Board Serial Number slot: Base Board Chassis Location *-firmware description: BIOS vendor: Packard Bell physical id: 0 version: V1.12 date: 07/11/2011 size: 1MiB capacity: 2496KiB capabilities: pci upgrade shadowing cdboot bootselect edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb biosbootspecification *-memory description: System Memory physical id: 1b slot: System board or motherboard size: 4GiB *-bank:0 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: NT2GC64B88B0NS-CG vendor: Nanya Technology physical id: 0 serial: 598E126E slot: ChannelA-DIMM0 size: 2GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: DIMM [empty] physical id: 1 slot: ChannelA-DIMM1 *-bank:2 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: NT2GC64B88B0NS-CG vendor: Nanya Technology physical id: 2 serial: 159E126C slot: ChannelB-DIMM0 size: 2GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:3 description: DIMM [empty] physical id: 3 slot: ChannelB-DIMM1 *-cpu description: CPU product: Intel(R) Core(TM) i3-2330M CPU @ 2.20GHz vendor: Intel Corp. physical id: 2e bus info: cpu@0 version: Intel(R) Core(TM) i3-2330M CPU @ 2.20GHz slot: CPU1 size: 2GHz capacity: 4GHz width: 64 bits clock: 1333MHz capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer xsave avx lahf_lm arat epb xsaveopt pln pts tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: cores=2 enabledcores=2 threads=4 *-cache:0 description: L1 cache physical id: 30 slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through instruction *-cache:1 description: L2 cache physical id: 31 slot: L2 Cache size: 256KiB capacity: 256KiB capabilities: synchronous internal write-through unified *-cache:2 description: L3 cache physical id: 32 slot: L3 Cache size: 3MiB capacity: 3MiB capabilities: synchronous internal write-through unified *-cache description: L1 cache physical id: 2f slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through data *-pci description: Host bridge product: 2nd Generation Core Processor Family DRAM Controller vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 09 width: 32 bits clock: 33MHz configuration: driver=agpgart-intel resources: irq:0 *-pci:0 description: PCI bridge product: Xeon E3-1200/2nd Generation Core Processor Family PCI Express Root Port vendor: Intel Corporation physical id: 1 bus info: pci@0000:00:01.0 version: 09 width: 32 bits clock: 33MHz capabilities: pci pm msi pciexpress normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:40 ioport:2000(size=4096) memory:d0000000-d10fffff ioport:a0000000(size=301989888) *-display description: VGA compatible controller product: NVIDIA Corporation vendor: NVIDIA Corporation physical id: 0 bus info: pci@0000:01:00.0 version: a1 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vga_controller bus_master cap_list rom configuration: driver=nvidia latency=0 resources: irq:16 memory:d0000000-d0ffffff memory:a0000000-afffffff memory:b0000000-b1ffffff ioport:2000(size=128) memory:d1000000-d107ffff *-display description: VGA compatible controller product: 2nd Generation Core Processor Family Integrated Graphics Controller vendor: Intel Corporation physical id: 2 bus info: pci@0000:00:02.0 version: 09 width: 64 bits clock: 33MHz capabilities: msi pm vga_controller bus_master cap_list rom configuration: driver=i915 latency=0 resources: irq:43 memory:d1400000-d17fffff memory:c0000000-cfffffff ioport:3000(size=64) *-communication description: Communication controller product: 6 Series/C200 Series Chipset Family MEI Controller #1 vendor: Intel Corporation physical id: 16 bus info: pci@0000:00:16.0 version: 04 width: 64 bits clock: 33MHz capabilities: pm msi bus_master cap_list configuration: driver=mei latency=0 resources: irq:42 memory:d1a04000-d1a0400f *-usb:0 description: USB controller product: 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #2 vendor: Intel Corporation physical id: 1a bus info: pci@0000:00:1a.0 version: 04 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:16 memory:d1a0a000-d1a0a3ff *-multimedia description: Audio device product: 6 Series/C200 Series Chipset Family High Definition Audio Controller vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 04 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:44 memory:d1a00000-d1a03fff *-pci:1 description: PCI bridge product: 6 Series/C200 Series Chipset Family PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: b4 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:17 memory:9fb00000-9fbfffff ioport:d1800000(size=1048576) *-network description: Ethernet interface product: NetLink BCM57785 Gigabit Ethernet PCIe vendor: Broadcom Corporation physical id: 0 bus info: pci@0000:02:00.0 logical name: eth0 version: 10 serial: b8:70:f4:e5:12:43 capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi msix pciexpress bus_master cap_list rom ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=tg3 driverversion=3.121 firmware=sb latency=0 link=no multicast=yes port=twisted pair resources: irq:16 memory:d1830000-d183ffff memory:d1840000-d184ffff memory:d1850000-d18507ff *-generic:0 description: SD Host controller product: NetXtreme BCM57765 Memory Card Reader vendor: Broadcom Corporation physical id: 0.1 bus info: pci@0000:02:00.1 version: 10 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=sdhci-pci latency=0 resources: irq:17 memory:d1800000-d180ffff *-generic:1 UNCLAIMED description: System peripheral product: Broadcom Corporation vendor: Broadcom Corporation physical id: 0.2 bus info: pci@0000:02:00.2 version: 10 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: latency=0 resources: memory:d1810000-d181ffff *-generic:2 UNCLAIMED description: System peripheral product: Broadcom Corporation vendor: Broadcom Corporation physical id: 0.3 bus info: pci@0000:02:00.3 version: 10 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: latency=0 resources: memory:d1820000-d182ffff *-pci:2 description: PCI bridge product: 6 Series/C200 Series Chipset Family PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: b4 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 memory:d1900000-d19fffff *-network description: Wireless interface product: BCM43225 802.11b/g/n vendor: Broadcom Corporation physical id: 0 bus info: pci@0000:03:00.0 logical name: eth1 version: 01 serial: 68:a3:c4:44:81:96 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=wl0 driverversion=5.100.82.38 ip=192.168.0.12 latency=0 multicast=yes wireless=IEEE 802.11bgn resources: irq:17 memory:d1900000-d1903fff *-usb:1 description: USB controller product: 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 04 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:23 memory:d1a09000-d1a093ff *-isa description: ISA bridge product: HM65 Express Chipset Family LPC Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 04 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: SATA controller product: 6 Series/C200 Series Chipset Family 6 port SATA AHCI Controller vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 logical name: scsi1 version: 04 width: 32 bits clock: 66MHz capabilities: storage msi pm ahci_1.0 bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:41 ioport:3098(size=8) ioport:30bc(size=4) ioport:3090(size=8) ioport:30b8(size=4) ioport:3060(size=32) memory:d1a08000-d1a087ff *-disk description: ATA Disk product: ST9500325AS vendor: Seagate physical id: 0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 0001 serial: S2W1AMSX size: 465GiB (500GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=a45f21e9 *-volume:0 description: Windows NTFS volume physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 version: 3.1 serial: 46aa-2a25 size: 19GiB capacity: 20GiB capabilities: primary ntfs initialized configuration: clustersize=4096 created=2011-08-25 21:32:00 filesystem=ntfs label=PQSERVICE state=clean *-volume:1 description: Windows NTFS volume physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 version: 3.1 serial: 10aa-ad1a size: 98MiB capacity: 100MiB capabilities: primary bootable ntfs initialized configuration: clustersize=4096 created=2011-08-25 21:32:03 filesystem=ntfs label=SYSTEM RESERVED state=clean *-volume:2 description: Windows NTFS volume physical id: 3 bus info: scsi@0:0.0.0,3 logical name: /dev/sda3 version: 3.1 serial: 668c5afc-182e-ff4b-b084-3cc09f54972d size: 395GiB capacity: 395GiB capabilities: primary ntfs initialized configuration: clustersize=4096 created=2011-08-25 21:32:03 filesystem=ntfs label=Don's Machine state=clean *-volume:3 description: Extended partition physical id: 4 bus info: scsi@0:0.0.0,4 logical name: /dev/sda4 size: 49GiB capacity: 49GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume:0 description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 3945MiB capabilities: nofs *-logicalvolume:1 description: Linux filesystem partition physical id: 6 logical name: /dev/sda6 logical name: / capacity: 46GiB configuration: mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,user_xattr,barrier=1,data=ordered state=mounted *-cdrom description: DVD-RAM writer product: DVD-RW DVRTD11RS vendor: PIONEER physical id: 1 bus info: scsi@1:0.0.0 logical name: /dev/cdrom logical name: /dev/cdrw logical name: /dev/dvd logical name: /dev/dvdrw logical name: /dev/sr0 version: 1.01 capabilities: removable audio cd-r cd-rw dvd dvd-r dvd-ram configuration: ansiversion=5 status=nodisc *-serial UNCLAIMED description: SMBus product: 6 Series/C200 Series Chipset Family SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 04 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:d1a06000-d1a060ff ioport:3040(size=32) *-power UNCLAIMED description: OEM_Define1 product: OEM_Define5 vendor: OEM_Define2 physical id: 1 version: OEM_Define6 serial: OEM_Define3 capacity: 75mWh *-battery description: Lithium Ion Battery product: CRB Battery 0 vendor: -Virtual Battery 0- physical id: 2 version: 10/12/2007 serial: Battery 0 slot: Fake

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  • Cross-Platform Mobile Development With Mono for Android and MonoTouch

    - by Wallym
    Many years ago, in fact pre-Java, I remember a hallway discussion about the desire to write a single application that could easily run across various platforms. At the time, we were only worried about writing applications on Windows 3.1 and Mac OS 7.x. There were many discussions about windows, user interface concepts, and specifically a rather long discussion as to whether Mac users would accept a Mac application that didn't have balloon help. Thankfully, the marketplace answered this question for us with the Windows API winning the battle.A similar set of questions is currently going on in the mobile world. Unfortunately, at this point in time, there is currently no winning API and none currently in sight. What's a developer to do? Here are some questions that developers have (and there are many more):How can mobile developers target Android and the iPhone with the same code?How can .NET developers share their code across Android, iPhone and other platforms?How can developers give applications the look and feel of the specific platform and still allow as much code as possible to be shared?Mobile devices share many common features, such as cameras, accelerometers, and address books. How can we take advantage of them in a platform independent way and still give the users the look of every other application running on their platform?In this article, we'll look at some solutions to these cross-platform and code-sharing questions between Mono for Android, MonoTouch and the .NET Framework available to developers. 

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  • Architect Day Artifacts

    - by Bob Rhubart
    In the last eight days the Oracle Technology Network Architect Day tour has stopped in Dallas, Anaheim (Disneyland, to be precise) , and at Oracle HQ in Redwood Shores,  CA. I was on-scene for the Dallas event, where I pulled a TMZ-style ambush on Chris Benedict from the Oracle Enterprise Solutions Group to capture this short video.     The other presenters escaped. But the slide decks from several of the presentations are now available on Slideshare:  IT Optimization: Reduce Data Center Costs and Set the Foundation for Future Growth as presented by Alan Levine, Oracle Enterprise Architect Senior Director Implementing Applications with SOA and Application Integration Architecture as presented by Vish Gaitonde, Director, Ecosystem Strategy, Application Integration Architecture Application Grid: Platform for Virtualization and Consolidation of Your Java Applications as presented by Sam Shah, Director, SOA and Integration, Oracle Enterprise Solutions Group Infrastructure Consolidation and Virtualization as presented by Steve Bennett, also a Director with the Oracle Enterprise Solutions Group Security in a Cloudy Architecture as presented by Geri Born, Security Specialist with the Oracle Enterprise Solutions Group I'll post more Architect Day presentations as soon as I track them down. A special thank you to Oracle ACE Directors Jordan Braunstein, Billy Tong, and Kai Yu, who were on hand in Dallas, and to fellow ACE Directors Basheer Khan and Floyd Teter for their participation in the Anaheim event.  (Floyd and his iPad came through again, allowing me to record the Anaheim panel discussion via Skype while sitting in my home office in Cleveland.) That audio, as well as audio from the panel discussion and a roundtable from the Dallas event, will be available soon as ArchBeat podcast programs. If you attended one of these events, a big thanks. Your active participation, your questions and input, are what these events are all about.  As new cities are added to the tour, we expect more of the same from the OTN architect community. And did I mention that the food is free? So stay tuned... del.icio.us Tags: oracle,otn,enterprise architecture,enterprise architect,archbeat,arch2arch,architect day Technorati Tags: oracle,otn,enterprise architecture,enterprise architect,archbeat,arch2arch,architect day   Cross-posted to the ArchBeat blog

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  • Architect Day Artifacts

    - by Bob Rhubart
    In the last eight days the Oracle Technology Network Architect Day tour has stopped in Dallas,  Anaheim (Disneyland, to be precise) , and at Oracle HQ in Redwood Shores,  CA. I was on-scene for the Dallas event, where I pulled a TMZ-style ambush on Chris Benedict from the Oracle Enterprise Solutions Group to capture this short video.     The other presenters escaped. But the slide decks from several of the presentations are now available on Slideshare:  IT Optimization: Reduce Data Center Costs and Set the Foundation for Future Growth as presented by Alan Levine, Oracle Enterprise Architect Senior Director Implementing Applications with SOA and Application Integration Architecture as presented by Vish Gaitonde, Director, Ecosystem Strategy, Application Integration Architecture Application Grid: Platform for Virtualization and Consolidation of Your Java Applications as presented by Sam Shah, Director, SOA and Integration, Oracle Enterprise Solutions Group Infrastructure Consolidation and Virtualization as presented by Steve Bennett, also a Director with the Oracle Enterprise Solutions Group Security in a Cloudy Architecture as presented by Geri Born, Security Specialist with the Oracle Enterprise Solutions Group I’ll post more Architect Day presentations as soon as I track them down. A special thank you to Oracle ACE Directors Jordan Braunstein, Billy Tong, and Kai Yu, who were on hand in Dallas, and to fellow ACE Directors Basheer Khan and Floyd Teter for their participation in the Anaheim event.  (Floyd and his iPad came through again, allowing me to record the Anaheim panel discussion via Skype while sitting in my home office in Cleveland.) That audio, as well as audio from the panel discussion and a roundtable from the Dallas event, will be available soon as ArchBeat podcast programs. If you attended one of these events, a big thanks. Your active participation, your questions and input, are what these events are all about.  As new cities are added to the tour, we expect more of the same from the OTN architect community. And did I mention that the food is free? So stay tuned… del.icio.us Tags: oracle,otn,enterprise architecture,enterprise architect,archbeat,arch2arch,architect day Technorati Tags: oracle,otn,enterprise architecture,enterprise architect,archbeat,arch2arch,architect day   Cross-posted to the Oracle Technology Network Blog

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  • Best of OTN - Week of August 10th

    - by CassandraClark-OTN
    Brief pubic service announcement before we get into the OTN community best of content for the week.... Four Bands. Three Epic Nights. Join Oracle for three evenings of entertainment and fun, all during Oracle OpenWorld and JavaOne, September 28-October 2, San Francisco. Learn More Architect Community Any discussion of the best of OTN must include the OTN ArchBeat Podcast. Consistently among the top 3 most popular Oracle podcasts, Archbeat focuses on real conversations with community members. Normally I pick the topics and the guest panelists for each program, but now you have a chance to take over that role and become a Guest Producer. In that role you'll pick the discussion topic and the panelists, while I do the all of the grunt work, allowing you to bask in the glory Want to know how to become an OTN ArchBeat Podcast Guest Producer? You'll find the details here: Yes, you can take over the OTN ArchBeat Podcast! And here are two examples of OTN ArchBeat Podcasts produced by community members: Data Warehousing and Oracle Data Integrator, from July 2013, was produced by Oracle ACE Director Gurcan Orhan, and features panelists Uli Bethke , Cameron Lackpour , and Michael Rainey . DevOps, Cloud, and Role Creep, from June 2013, was produced by Oracle ACE Director Ron Batra and features panelists Basheer Khan and Cary Millsap -- OTN Architect Community Manager Bob Rhubart Database Community OTN DBA/DEV Watercooler Blog - Did You Say "JSON Support" in Oracle 12.1.0.2?. -- OTN Database Community Manager Laura Ramsey Java Community The Java Source Blog - walkmod : A Tool to Apply Coding Conventions . Friday Funny: I was worried the #NSA might be spying on me Thanks, @pacohope. -- OTN Java Community Manager Tori Weildt Systems Community The OTN Systems Community HomePage- Find Great Resources for System Admins and Developers. -- OTN Systems Community Manager Rick Ramsey

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  • USB Mouse and Keyboard not working in Linux 4 Tegra

    - by Sijo
    I am a new person in Tegra Linux development. I have Tamontem NG Evaluation board with Tegra 3 Chip. I installed L4T sample file system from NVIDIA tegra Resources (https://developer.nvidia.com/linux-tegra) and installed the file system as described in the documentation provided in NVIDIA site. Already these was an SD card with L4T running. i dont want to change the boot loader. So I copied the boot.scr.uimg to root (/) folder and uImage to boot(/boot/) and it starts booting from the existing SD card. After that while booting, some errors occurred in some Bluetooth devices (there is no bluetooth device in the board). So I disabled Bluetooth by giving the following command sudo mv /etc/init/bluetooth.conf /etc/init/bluetooth.conf.noexec Now the problem is that mouse and keyboard are not working. So i cannot login. Even though i installed desktop, the mouse and keyboard are not working. But mouse and keyboard are enumerating. lsusb command is showing the USB mouse and keyboard. The installed file system is Ubuntu 13.04. Linux Kernel version is 3.1 What to do. Please help.Thanks in Advance.

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  • New META TAGS with positive effects for seo ranking in 2011 and beyond

    - by Sam
    Hi all, im trying to make an up to date chart of meta tags, for all of us, with their purposes, their use and their good (or bad) effects on search engines/being found. Also any body knows new/promising meta tags? I will add yours into my list so this chart is a result of live discussion and up to date. Also, it would be creative to invent your own useful meta, because we are the ones making the web, or aren't we? LEGEND P PURPOSE? What does this meta tag do in 2011, if anything N NECESSARY? Does every site really needs it or not? G GOOD wether it will have a good effect for your site to be found I INVENTED meta tag, who knows it will be accepted in a year! META "METANAME" = PURPOSE? - NECESSARY? - GOOD EFFECT? #### important meta "title" = P consice summary + teaser - N very - G extremely meta "description" = P description + teaser - N yes - G very meta "robots" = P if needed, to skip default dmoz/yahoodir listing - N no - G? #### new & promising! Thanks for input (John, ) meta "original-source" P url of whoever broke the news gets credits - N? - G? meta "syndication-source" P url for syndication of published news - N? - G? meta "canonical" P? - N? - G? #### seems obsolete meta "keywords" = P some keywords - N+G not for google but yahoo likes them meta "language" = P overrule guesswork by defining language - N no - G? meta "page-topic" = P topic/theme - N? - G? meta "abstract" = P short summary - N? - G? meta "copyright" = ? #### invented by me meta "audience" = P filteres audience: "+seniors, +parents, -children, -youth" meta "mood" = P specifies textual style: "discussion, informative, commercial, sexual, fictional, scientific, romantic, therapeutic, technical"

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  • What ways are there to determine if an idea for change is viable or not?

    - by Kenneth
    A recent discussion on here about whether or not program windows should still be called screens or if we should have improved terminology got me thinking... Dangerous I know! People as a whole tend to be fairly resistant to change. We get comfortable in our niches and used to the way things are. While some changes lead to good results and improve our lives or the way things are done, others are clearly not enough of a change or overall bad and not even worth attempting. What guides can we use as we program to determine if an improvement (whether it be to coding style, terminology, user interface, language use, etc) is really an improvement or not? I'm sure to some extent nothing will replace the try-it-out approach but are there any tests or guides that can be used to eliminate certain ideas that would eventually turn out to be worthless or a waste of time to pursue? EDIT: For anyone who is wondering the discussion that brought this question up in my mind is found here: Does your organization still use the term "screens" to describe a user interface?

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  • ArchBeat Link-o-Rama for November 21, 2012

    - by Bob Rhubart
    Fault Handling and Prevention - Part 1 | Guido Schmutz and Ronald van Luttikhuizen In this technical article, part one of a four part series, Oracle ACE Directors Guido Schmutz and Ronald van Luttikhuizen guide you through an introduction to fault handling in a service-oriented environment using Oracle SOA Suite and Oracle Service Bus. One Stop Shop for Oracle Webcasts Webcasts can be a great way to get information about Oracle products without having to go cross-eyed reading yet another document off your computer screen. Oracle's new Webcast Center offers selectable filtering to make it easy to get to the information you want. Yes, you have to register to gain access, but that process is quick, and with over 200 webcasts to choose from you know you'll find useful content. Oracle on Oracle: Is that all? (Identity Management)| Darin Pendergraft Darin Pendergraft shares a discussion with Jaime Cardoso aboutthe latter's experience with Oracle's IDM products. What's particularly interesting is that the discussion grew out of Jaime's highly critical comment that Darin missed important pointsabout those products in an earlier interview Chirag Andani. If that ain't social engagement, I don't know what is. I.T. Chargeback : Core to Cloud Computing | Zero to Cloud "While chargeback has existed as a concept for many years (especially in mainframe environments), it is the move to this self-service model that has created a need for a new breed of chargeback applications for cloud," says Mark McGill. "Enabling self-service without some form of chargeback is like opening a shop where all of the goods are free." New Self-paced Online Oracle BPM 11g Developer Training | Dan Atwood Oracle ACE Dan Atwood of Avio Consulting shares a lot of information about a new Oracle BPM 11g Developer Workshop. JPA SQL and Fetching tuning ( EclipseLink ) | Edwin Biemond Oracle ACE Edwin Biemond's post illustrates how to "use the department and employee entity of the HR Oracle demo schema to explain the JPA options you have to control the SQL statements and the JPA relation Fetching." Thought for the Day "Team development is like a birthday cake. Everybody gets a piece." — Assaad Chalhoub Source: SoftwareQuotes.com

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  • Checkers AI Algorithm

    - by John
    I am making an AI for my checkers game and I'm trying to make it as hard as possible. Here is the current criteria for a move on the hardest difficulty: 1: Look For A Block: This is when a piece is being threatened and another piece can be moved in behind it to protect it. Here is an example: Black Moves |W| |W| |W| |W| | | |W| |W| |W| |W| |W| | | |W| |W| | | | | |W| | | | | | | | | |B| | | | | |B| | | |B| |B| |B| |B| |B| |B| | | |B| |B| |B| |B| White Blocks |W| |W| |W| |W| | | |W| | | |W| |W| |W| |W| |W| |W| | | | | |W| | | | | | | | | |B| | | | | |B| | | |B| |B| |B| |B| |B| |B| | | |B| |B| |B| |B| 2: Move pieces out of danger: if any piece is being threatened, and a piece cannot block for that piece, then it will attempt to move out of the way. If the piece cannot move out of the way without still being in danger, the computer ignores the piece. 3: If the computer player owns any kings, it will attempt to 'hunt down' enemy pieces on the board, if no moves can be made that won't in danger the king or any other pieces, the computer ignores this rule. 4: Any piece that is owned by the computer that is in column 1 or 6 will attempt to go to a side. When a piece is in column 0 or 7, it is in a very strategic position because it cannot get captured while it is in either of these columns 5: It makes an educated random move, the move will not indanger the piece that is moving or any piece that is on the board. 6: If none of the above are possible it makes a random move. This question is not really specific to any language but if all examples could be in Java that would be great, considering this app is written in android. Does anyone see any room for improvement in this algorithm? Anything that would make it better at playing checkers?

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  • Separation of development responsibilities in a new project

    - by dreza
    We have very recently started a new project (MVC 3.0) and some of our early discussion has been around how the work and development will be split amongst the team members to ensure we get the least amount of overlap of work and so help make it a bit easier for each developer to get on and do their work. The project is expected to take about 6 months - 1 year (although not all developers are likely to be on and might filter off towards the end), Our team is going to be small so this will help out a bit I believe. The team will essentially consist of: 3 x developers (All different levels i.e. more senior, intermediate and junior) 1 x project manager / product owner / tester An external company responsbile for doing our design work General project/development decisions so far have included: Develop in an Agile way using SCRUM techniques (We are still very much learning this approach as a company) Use MVVM archectecture Use Ninject and DI where possible Attempt to use as TDD as much as possible to drive development. Keep our controllers as skinny as possible Keep our views as simple as possible During our discussions two approaches have been broached as too how to seperate the workload given our objectives outlined above. OPTION 1: A framework seperation where each person is responsible for conceptual areas with overlap and discussion primarily in the integration areas. The integration areas would the responsibily of both developers as required. View prototypes (**Graphic designer**) | - Mockups | Views (Razor and view helpers etc) & Javascript (**Developer 1**) | - View models (Integration point) | Controllers and Application logic (**Developer 2**) | - Models (Integration point) | Domain model and persistence (**Developer 3**) OPTION 2: A more task orientated approach where each person is responsible for the completion of the entire task (story) from view - controller - model. QUESTION: For those who have worked in small teams developing MVC projects how have you managed the workload distribution in this situation. I can't imagine the junior would be responsible for building parts of the underlying architecture so would given them responsibility for the view make sense considering we are trying to keep it simple?

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  • One page using querystring or many folders and pages?

    - by ClarkeyBoy
    I have an application where I have the 'core' code in one folder for which there is a virtual directory in the root, such that I can include any core files using /myApp/core/bla.asp. I then have two folders outside of this with a default.asp which currently use the querystring to define what page should be displayed. One page is for general users, the other will only be accessible to users who have permission to manage users / usergroups / permissions. The core code checks the querystring and then checks the permissions for that user. An example of this as it is now is default.asp?action=view&viewtype=list&objectid=server. I am not worried about SEO as this is an internal app and uses Windows Auth. My question is, is it better the way it is now or would it be better to have something like the following: /server/view/list/ /server/view/?id=123 /server/create/ /server/edit/?id=123 /server/remove/?id=123 In the above folders I would have a home page which defines all the variables which are currently determined by the querystring - in /server/create/ for example, I would define the action as 'create', object name as 'server' and so on. In terms of future development, I really have no idea which method would be best. I think the 2nd method would be best in terms of following what page does what but this is such a huge change to make at this stage that I would really like some opinions, preferably based on experience. PS Sorry if the tags are wrong - I am new to this forum and thought this was a bit too much of a discussion for StackOverflow as that is very much right / wrong answer based. I got the idea SE is more discussion based.

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