how to store data in ram in verilog
- by anum
i am having a bit stream of 128 bits @ each posedge of clk,i.e.total 10 bit streams each of length 128 bits.
i want to divide the 128 bit stream into 8, 8 bits n hve to store them in a ram / memory of width 8 bits.
i did it by assigning 8, 8 bits to wires of size 8 bit.in this way there are 16 wires.
and i am using dual port ram...wen i cal module of memory in stimulus.i don know how to give input....as i am hving 16 different wires naming from k1 to k16.
**codeeee**
// this is stimulus file
module final_stim;
reg [7:0] in,in_data;
reg clk,rst_n,rd,wr,rd_data,wr_data;
wire [7:0] out,out_wr, ouut;
wire[7:0] d;
integer i;
//wire[7:0] xor_out;
reg kld,f;
reg [127:0]key;
wire [127:0] key_expand;
wire [7:0]out_data;
reg [7:0] k;
//wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;
wire [7:0] out_data1;
**//key_expand is da output which is giving 10 streams of size 128 bits.**
assign k1=key_expand[127:120];
assign k2=key_expand[119:112];
assign k3=key_expand[111:104];
assign k4=key_expand[103:96];
assign k5=key_expand[95:88];
assign k6=key_expand[87:80];
assign k7=key_expand[79:72];
assign k8=key_expand[71:64];
assign k9=key_expand[63:56];
assign k10=key_expand[55:48];
assign k11=key_expand[47:40];
assign k12=key_expand[39:32];
assign k13=key_expand[31:24];
assign k14=key_expand[23:16];
assign k15=key_expand[15:8];
assign k16=key_expand[7:0];
**// then the module of memory is instanciated.
//here k1 is sent as input.but i don know how to save the other values of k.
//i tried to use for loop but it dint help**
memory m1(clk,rst_n,rd, wr,k1,out_data1);
aes_sbox b(out,d);
initial
begin
clk=1'b1;
rst_n=1'b0;
#20
rst_n = 1;
//rd=1'b1;
wr_data=1'b1;
in=8'hd4;
#20
//rst_n=1'b1;
in=8'h27;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h11;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hae;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'he0;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hbf;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h98;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hf1;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hb8;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'hb4;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h5d;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'he5;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h1e;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h41;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h52;
rd_data=1'b0;
wr_data=1'b1;
#20
in=8'h30;
rd_data=1'b0;
wr_data=1'b1;
#20
wr_data=1'b0;
#380
rd_data=1'b1;
#320
rd_data = 1'b0;
///////////////
#10
kld = 1'b1;
key=128'h 2b7e151628aed2a6abf7158809cf4f3c;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b0;
#10
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
kld = 1'b0;
key = 128'h 2b7e151628aed2a6abf7158809cf4f3c;
wr = 1'b1;
rd = 1'b1;
#20
wr = 1'b0;
#20
rd = 1'b1;
#4880
f=1'b1;
/////////////////////////////////////////////////
// out_data[i]
end
/*always@(*)
begin
while(i)
mem[i]^mem1[i] ;
i<=16;
break;
end*/
always
#10 clk=~clk;
always@(posedge clk)
begin
//$monitor($time," out_wr=%h,out_rd=%h\n ",out_wr,out);
#10000
$stop;
end
endmodule
