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  • iPhone: Grouping records in multiple UITableView views

    - by Nic Hubbard
    Let me first say, I know how to create sections and group records within a UITableView. What I am wanting to do is something similar to creating a photo album. So, I have all my data objects coming from core data, and, I want to be able to create a custom group, such as "My Trip to Mexico" and "First Birthday". Then, the user should be able to add objects/records into new sections/albums. So, basically the user is creating custom sections with their own custom names, and then choosing what records should go into that section/album. So, I am just wondering what is the best way to do this? I am thinking that I would just create some extra attributes for my core data model. Or, would I create a whole new "Album Section" object, and somehow use that? Point me in the right direction. :)

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  • Fault exception trashes a register causing a crash in [NSInvocation invoke]

    - by Mike Weller
    I have an NSOperation which fetches some objects from a core data persistent store and sums up a few totals. Sometimes an object is deleted while the operation in in progress, so a core data fault exception occurs. I try/catch the exception while summing to ignore it because I just want to skip objects that cannot be faulted in. However, when one of these fault exceptions occurs (and I swallow it) there is a crash after the invocation returns in [NSInvocation invoke]. It's a bad memory access when dereferencing the value in r10 which according to GDB on a successful run points to one of these: (gdb) x 0x38388348 0x38388348 <OBJC_IVAR_$_NSInvocation._retdata>: 0x00000008 If a fault exception occured a value of 0x02 is in the register which causes the crash. A quick google search tells me that r10 should be saved by the callee, meaning it is not being restored by whatever code is changing it when this exception occurs. Can anybody explain this? I'm not an expert when it comes to these kinds of low-level details

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  • Should I create subclass NSManagedObject or not?

    - by TP
    Hi, I have spent a few days learning and writing NSCoding and finally got it working. However, it took very long to archive and unarchive the (quite complex) object graph, which is unacceptable. After searching the internet for some time, I think the better way is to use core data. Do you recommend that 1) I should rewrite all my classes as subclasses of NSManagedObject or 2) should I create an instance variable of NSManagedObject in each of my class so that any changes to the class also updates its core data representation? Doing either way will need significant changes to the exiting classes and I think I have to update lots of unit test cases as well if it changes the way the classes are initialized. What do you recommend? I really don't want to head to the wrong approach again... Thanks!

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  • Non US characters in section headers for a UITableView

    - by epatel
    I have added a section list for a simple Core Data iPhone app. I followed this so question to create it - How to use the first character as a section name but my list also contain items starting with characters outside A-Z, specially Å,Ä and Ö used here in Sweden. The problem now is that when the table view shows the section list the three last characters are drawn wrong. See image below It seems like my best option right now is to let those items be sorted under 'Z' if ([letter isEqual:@"Å"] || [letter isEqual:@"Ä"] || [letter isEqual:@"Ö"]) letter = @"Z"; Someone that have figured this one out? And while I'm at it... 'Å', 'Ä' and 'Ö' should be sorted in that order but are sorted as 'Ä', 'Å' and 'Ö' by Core Data NSSortDescriptor. I have tried to set set the selector to localizedCaseInsensitiveCompare: but that gives a out of order section name 'Ä. Objects must be sorted by section name' error. Seen that too?

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  • mx.core::BitmapAsset could not be found

    - by asksuperuser
    I tried the code EmbedAssets.as below found in sample here: http://www.senocular.com/flash/tutorials/as3withmxmlc/ I got this error when building with mxmlc.exe and testing the ouput EmbedAssets.swf in Flash Player 9: VerifyError: Error #1014: mx.core::BitmapAsset could not be found package { import flash.display.Sprite; public class EmbedAssets extends Sprite { [Embed(source="images/trophy.png")] private var TrophyImage:Class; [Embed(source="swfs/satdish.swf")] private var SatelliteAnimation:Class; public function EmbedAssets() { addChild(new SatelliteAnimation()); addChild(new TrophyImage()); } } } satdish.swf is not corrupted so I don't understand why this error message.

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  • How do I get the CoreData Debug argument to output to the console?

    - by radesix
    According to Apple documentation on debugging Core Data it says we should be able to pass an argument to the application which will output the SQL core data sends to SQLite. I have gone into the arguments tab of my executable in XCode and specified the argument: -com.apple.CoreData.SQLDebug 1 However, I see no SQL in the console. I then tried to use this parameter in the CoreDataBooks application provided by Apple just in case there was some other issue in MY program. Even in Apple's example I get no SQL output in the console. Am I doing something wrong? Is Apple's documentation wrong? Should I be looking someplace other than the console? Has anyone else had success with this argument?

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  • How to store array of NSManagedObjects in an NSManagedObject

    - by David Tay
    I am loading my app with a property list of data from a web site. This property list file contains an NSArray of NSDictionaries which itself contains an NSArray of NSDictionaries. Basically, I'm trying to load a tableView of restaurant menu categories each of which contains menu items. My property list file is fine. I am able to load the file and loop through the nodes structure creating NSEntityDescriptions and am able to save to Core Data. Everything works fine and expectedly except that in my menu category managed object, I have an NSArray of menu items for that category. Later on, when I fetch the categories, the pointers to the menu items in a category is lost and I get all the menu items. Am I suppose to be using predicates or does Core Data keep track of my object graph for me? Can anyone look at how I am loading Core Data and point out the flaw in my logic? I'm pretty good with either SQL and OOP by themselves, but am a little bewildered by ORM. I thought that I should just be able to use aggregation in my managed objects and that the framework would keep track of the pointers for me, but apparently not. NSError *error; NSURL *url = [NSURL URLWithString:@"http://foo.com"]; NSArray *categories = [[NSArray alloc] initWithContentsOfURL:url]; NSMutableArray *menuCategories = [[NSMutableArray alloc] init]; for (int i=0; i<[categories count]; i++){ MenuCategory *menuCategory = [NSEntityDescription insertNewObjectForEntityForName:@"MenuCategory" inManagedObjectContext:[self managedObjectContext]]; NSDictionary *category = [categories objectAtIndex:i]; menuCategory.name = [category objectForKey:@"name"]; NSArray *items = [category objectForKey:@"items"]; NSMutableArray *menuItems = [[NSMutableArray alloc] init]; for (int j=0; j<[items count]; j++){ MenuItem *menuItem = [NSEntityDescription insertNewObjectForEntityForName:@"MenuItem" inManagedObjectContext:[self managedObjectContext]]; NSDictionary *item = [items objectAtIndex:j]; menuItem.name = [item objectForKey:@"name"]; menuItem.price = [item objectForKey:@"price"]; menuItem.image = [item objectForKey:@"image"]; menuItem.details = [item objectForKey:@"details"]; [menuItems addObject:menuItem]; } [menuCategory setValue:menuItems forKey:@"menuItems"]; [menuCategories addObject:menuCategory]; [menuItems release]; } if (![[self managedObjectContext] save:&error]) { NSLog(@"An error occurred: %@", [error localizedDescription]); }

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  • Aborted core dumped C++

    - by avd
    I have a large C++ function which uses OpenCV library and running on Windows with cygwin g++ compiler. At the end it gives Aborted(core dumped) but the function runs completely before that. I have also tried to put the print statement in the end of the function. That also gets printed. So I think there is no logical bug in code which will generate the fault. Please explain. I am also using assert statements.But the aborted error is not due to assert statement. It does not say that assertion failed. It comes at end only without any message. Also the file is a part of a large project so I cannot post the code also.

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  • Why would I want to have a non-standard attribute?

    - by dontWatchMyProfile
    The documentation on Core Data entities says: You might implement a custom class, for example, to provide custom accessor or validation methods, to use non-standard attributes, to specify dependent keys, to calculate derived values, or to implement any other custom logic. I stumbled over the non-standard attributes claim. It's just a guess: If my attribute is anything other than NSString, NSNumber or NSDate I will want to have a non-standard Attribute with special setter and getter methods? So, for example, if I wanted to store an image, this would be a non-standard Attribute with type NSData and a special method, say -(void)setImageWithFileURL:(NSURL*)url which then pulls the image data from the file, puts in in an NSData and assigns it to core data? Or did I get that wrong?

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  • Read Core data in Serial Queue for iPhone app

    - by user1277209
    I have an app which uses Core data and the values are fetched from a link on internet. This runs absolutely fine when I am creating a serial queue in AppDelegate and I am not facing any problem with the same. Now, when I am trying to re-create similar scenario in a UITableViewController and executing the same in a serial queue but when the control reaches NSError *error; NSArray *match = [context executeFetchRequest:fetchRequest error:&error]; execution control disappears and then this code remains in the execution till eternity. Can anyone help me with what exactly is wrong here? FYI, I am passing the same ManagedObjectContext to the serial queue.

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  • Is there a way to force CoreImage to use the GPU?

    - by NSSplendid
    We are having the following problem: a series of Core Image filters runs constantly in our program. When evaluating on my Macbook Pro, Core Image decides to schedule all graphics computation on the GPU, as expected. When using a MacPro, however, CI uses the CPUs! This is a problem, as we need them for other processing. [1] The question now is: Can one tell CI to run exclusively on the GPU? [1] Both hardware sets are of the newest kind. The MacPro has 8 Cores.

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  • I have a Segmentation fault (core dumped) when using strcpy, malloc, and struct

    - by malsh002
    Okay, when I run this code, I have a segmentation fault #include<stdio.h> #include<stdlib.h> #include<string.h> #define MAX 64 struct example { char *name; }; int main() { struct example *s = malloc (MAX); strcpy(s->name ,"Hello World!!"); return !printf("%s\n", s->name); } the terminal output: alshamlan@alshamlan-VGN-CR520E:/tmp/interview$ make q1 cc -Wall -g q1.c -o q1 alshamlan@alshamlan-VGN-CR520E:/tmp/interview$ ./q1 Segmentation fault (core dumped) alshamlan@alshamlan-VGN-CR520E:/tmp/interview$ gedit q1.c Can someone explain what's going on? thanks.

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  • Linux e1000e (Intel networking driver) problems galore, where do I start?

    - by Evan Carroll
    I'm currently having a major problem with e1000e (not working at all) in Ubuntu Maverick (1.0.2-k4), after resume I'm getting a lot of stuff in dmesg: [ 9085.820197] e1000e 0000:02:00.0: PCI INT A disabled [ 9089.907756] e1000e: Intel(R) PRO/1000 Network Driver - 1.0.2-k4 [ 9089.907762] e1000e: Copyright (c) 1999 - 2009 Intel Corporation. [ 9089.907797] e1000e 0000:02:00.0: Disabling ASPM L1 [ 9089.907827] e1000e 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 9089.907857] e1000e 0000:02:00.0: setting latency timer to 64 [ 9089.908529] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X [ 9089.908922] e1000e 0000:02:00.0: Disabling ASPM L0s [ 9089.908954] e1000e 0000:02:00.0: (unregistered net_device): PHY reset is blocked due to SOL/IDER session. [ 9090.024625] e1000e 0000:02:00.0: eth0: (PCI Express:2.5GB/s:Width x1) 00:0a:e4:3e:ce:74 [ 9090.024630] e1000e 0000:02:00.0: eth0: Intel(R) PRO/1000 Network Connection [ 9090.024712] e1000e 0000:02:00.0: eth0: MAC: 2, PHY: 2, PBA No: 005302-003 [ 9090.109492] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X [ 9090.164219] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X and, a bunch of [ 2128.005447] e1000e 0000:02:00.0: eth0: Detected Hardware Unit Hang: [ 2128.005452] TDH <89> [ 2128.005454] TDT <27> [ 2128.005456] next_to_use <27> [ 2128.005458] next_to_clean <88> [ 2128.005460] buffer_info[next_to_clean]: [ 2128.005463] time_stamp <6e608> [ 2128.005465] next_to_watch <8a> [ 2128.005467] jiffies <6f929> [ 2128.005469] next_to_watch.status <0> [ 2128.005471] MAC Status <80080703> [ 2128.005473] PHY Status <796d> [ 2128.005475] PHY 1000BASE-T Status <4000> [ 2128.005477] PHY Extended Status <3000> [ 2128.005480] PCI Status <10> I decided to compile the latest stable e1000e to 1.2.17, now I'm getting: [ 9895.678050] e1000e: Intel(R) PRO/1000 Network Driver - 1.2.17-NAPI [ 9895.678055] e1000e: Copyright(c) 1999 - 2010 Intel Corporation. [ 9895.678098] e1000e 0000:02:00.0: Disabling ASPM L1 [ 9895.678129] e1000e 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 9895.678162] e1000e 0000:02:00.0: setting latency timer to 64 [ 9895.679136] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X [ 9895.679160] e1000e 0000:02:00.0: Disabling ASPM L0s [ 9895.679192] e1000e 0000:02:00.0: (unregistered net_device): PHY reset is blocked due to SOL/IDER session. [ 9895.791758] e1000e 0000:02:00.0: eth0: (PCI Express:2.5GB/s:Width x1) 00:0a:e4:3e:ce:74 [ 9895.791766] e1000e 0000:02:00.0: eth0: Intel(R) PRO/1000 Network Connection [ 9895.791850] e1000e 0000:02:00.0: eth0: MAC: 3, PHY: 2, PBA No: 005302-003 [ 9895.892464] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X [ 9895.948175] e1000e 0000:02:00.0: irq 44 for MSI/MSI-X [ 9895.949111] ADDRCONF(NETDEV_UP): eth0: link is not ready [ 9895.954694] e1000e: eth0 NIC Link is Up 10 Mbps Full Duplex, Flow Control: RX/TX [ 9895.954703] e1000e 0000:02:00.0: eth0: 10/100 speed: disabling TSO [ 9895.955157] ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 9906.832056] eth0: no IPv6 routers present With 1.2.20 I get: [ 9711.525465] e1000e: Intel(R) PRO/1000 Network Driver - 1.2.20-NAPI [ 9711.525472] e1000e: Copyright(c) 1999 - 2010 Intel Corporation. [ 9711.525521] e1000e 0000:02:00.0: Disabling ASPM L1 [ 9711.525554] e1000e 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 9711.525586] e1000e 0000:02:00.0: setting latency timer to 64 [ 9711.526460] e1000e 0000:02:00.0: irq 45 for MSI/MSI-X [ 9711.526487] e1000e 0000:02:00.0: Disabling ASPM L0s [ 9711.526523] e1000e 0000:02:00.0: (unregistered net_device): PHY reset is blocked due to SOL/IDER session. [ 9711.639763] e1000e 0000:02:00.0: eth0: (PCI Express:2.5GB/s:Width x1) 00:0a:e4:3e:ce:74 [ 9711.639771] e1000e 0000:02:00.0: eth0: Intel(R) PRO/1000 Network Connection [ 9711.639854] e1000e 0000:02:00.0: eth0: MAC: 3, PHY: 2, PBA No: 005302-003 [ 9712.060770] e1000e 0000:02:00.0: irq 45 for MSI/MSI-X [ 9712.116195] e1000e 0000:02:00.0: irq 45 for MSI/MSI-X [ 9712.117098] ADDRCONF(NETDEV_UP): eth0: link is not ready [ 9712.122684] e1000e: eth0 NIC Link is Up 100 Mbps Full Duplex, Flow Control: RX/TX [ 9712.122693] e1000e 0000:02:00.0: eth0: 10/100 speed: disabling TSO [ 9712.123142] ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 9722.920014] eth0: no IPv6 routers present But, I'm still getting these [ 9982.992851] PCI Status <10> [ 9984.993602] e1000e 0000:02:00.0: eth0: Detected Hardware Unit Hang: [ 9984.993606] TDH <5d> [ 9984.993608] TDT <6b> [ 9984.993611] next_to_use <6b> [ 9984.993613] next_to_clean <5b> [ 9984.993615] buffer_info[next_to_clean]: [ 9984.993617] time_stamp <24da80> [ 9984.993619] next_to_watch <5d> [ 9984.993621] jiffies <24f200> [ 9984.993624] next_to_watch.status <0> [ 9984.993626] MAC Status <80080703> [ 9984.993628] PHY Status <796d> [ 9984.993630] PHY 1000BASE-T Status <4000> [ 9984.993632] PHY Extended Status <3000> [ 9984.993635] PCI Status <10> [ 9986.001047] e1000e 0000:02:00.0: eth0: Reset adapter [ 9986.176202] e1000e: eth0 NIC Link is Up 10 Mbps Full Duplex, Flow Control: RX/TX [ 9986.176211] e1000e 0000:02:00.0: eth0: 10/100 speed: disabling TSO I'm not sure where to start troubleshooting this. Any ideas? Here is the result of ethtool -d eth0 MAC Registers ------------- 0x00000: CTRL (Device control register) 0x18100248 Endian mode (buffers): little Link reset: reset Set link up: 1 Invert Loss-Of-Signal: no Receive flow control: enabled Transmit flow control: enabled VLAN mode: disabled Auto speed detect: disabled Speed select: 1000Mb/s Force speed: no Force duplex: no 0x00008: STATUS (Device status register) 0x80080703 Duplex: full Link up: link config TBI mode: disabled Link speed: 10Mb/s Bus type: PCI Express Port number: 0 0x00100: RCTL (Receive control register) 0x04048002 Receiver: enabled Store bad packets: disabled Unicast promiscuous: disabled Multicast promiscuous: disabled Long packet: disabled Descriptor minimum threshold size: 1/2 Broadcast accept mode: accept VLAN filter: enabled Canonical form indicator: disabled Discard pause frames: filtered Pass MAC control frames: don't pass Receive buffer size: 2048 0x02808: RDLEN (Receive desc length) 0x00001000 0x02810: RDH (Receive desc head) 0x00000001 0x02818: RDT (Receive desc tail) 0x000000F0 0x02820: RDTR (Receive delay timer) 0x00000000 0x00400: TCTL (Transmit ctrl register) 0x3103F0FA Transmitter: enabled Pad short packets: enabled Software XOFF Transmission: disabled Re-transmit on late collision: enabled 0x03808: TDLEN (Transmit desc length) 0x00001000 0x03810: TDH (Transmit desc head) 0x00000000 0x03818: TDT (Transmit desc tail) 0x00000000 0x03820: TIDV (Transmit delay timer) 0x00000008 PHY type: IGP2 and ethtool -c eth0 Coalesce parameters for eth0: Adaptive RX: off TX: off stats-block-usecs: 0 sample-interval: 0 pkt-rate-low: 0 pkt-rate-high: 0 rx-usecs: 3 rx-frames: 0 rx-usecs-irq: 0 rx-frames-irq: 0 tx-usecs: 0 tx-frames: 0 tx-usecs-irq: 0 tx-frames-irq: 0 rx-usecs-low: 0 rx-frame-low: 0 tx-usecs-low: 0 tx-frame-low: 0 rx-usecs-high: 0 rx-frame-high: 0 tx-usecs-high: 0 tx-frame-high: 0 Here is also the lspci -vvv for this controller 02:00.0 Ethernet controller: Intel Corporation 82573L Gigabit Ethernet Controller Subsystem: Lenovo ThinkPad X60s Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 45 Region 0: Memory at ee000000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at 2000 [size=32] Capabilities: [c8] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 415a Capabilities: [e0] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <128ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number 00-0a-e4-ff-ff-3e-ce-74 Kernel driver in use: e1000e Kernel modules: e1000e I filed a bug on this upstream, still no idea how to get more useful information. Here is a the result of the running that script EEPROM FIX UPDATE $ sudo bash fixeep-82573-dspd.sh eth0 eth0: is a "82573L Gigabit Ethernet Controller" This fixup is applicable to your hardware Your eeprom is up to date, no changes were made Do I still need to do anything? Also here is my EEPROM dump $ sudo ethtool -e eth0 Offset Values ------ ------ 0x0000 00 0a e4 3e ce 74 30 0b b2 ff 51 00 ff ff ff ff 0x0010 53 00 03 02 6b 02 7e 20 aa 17 9a 10 86 80 df 80 0x0020 00 00 00 20 54 7e 00 00 14 00 da 00 04 00 00 27 0x0030 c9 6c 50 31 3e 07 0b 04 8b 29 00 00 00 f0 02 0f 0x0040 08 10 00 00 04 0f ff 7f 01 4d ff ff ff ff ff ff 0x0050 14 00 1d 00 14 00 1d 00 af aa 1e 00 00 00 1d 00 0x0060 00 01 00 40 1f 12 07 40 ff ff ff ff ff ff ff ff 0x0070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 4a e0 I'd also like to note that I used eth0 every day for years and until recently never had an issue.

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  • L'Internet en 3D arrivera d'ici 5 ans d'après Intel, est-ce le futur du web ?

    L'Internet en 3D arrivera d'ici 5 ans d'après Intel, est-ce le futur du web ? Sean Koehl travaille chez Intel en tant que "techno évangéliste". Il s'est réccemment exprimé au sujet du futur d'Internet, et il estime que le réseau "sera complètement différent d'ici 5 à 10 ans". Selon lui, notre manière d'interagir entre nous, et avec des appareils électroniques, va changer. Radicalement. Ainsi, il prédit l'émergence d'une technologie tri-dimensionnelle très réaliste dans 5 ans. Comme de plus en plus de gens autour du monde s'équipent avec des ordinateurs ou des smartphones et ont un accès à l'Internet. Sean explique qu'on commence seulement à exploiter toute cette puissance informatiq...

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  • Intel dévoile un PC avec un processeur à 48 coeurs, les fondeurs se rendent coup pour coup dans la c

    Mise à jour du 09/04/10 Intel dévoile un PC avec un processeur à 48 coeurs Les fondeurs se rendent coup pour coup dans la course au multi-coeur Après le prototype pour serveur, la mise en application en desktop. Sean Koehl, "techno évangéliste" de l'Intel Labs, vient de dévoiler un ordinateur particulièrement performant puisque celui-ci embarque un processeur à... 48 coeurs ! (lire ci-avant) Arrêtons le suspens, le grand public n'est pas visé (en tout cas pas tout de suite). Les premiers exemplaires de ces machines seront livrés vers mi-2010 à des institutions spécialisées dans la recherche. Sean Koehl note né...

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  • How Do You Calculate Processor Speed on Multi-core Processors?

    - by Jason Fitzpatrick
    The advent of economical consumer grade multi-core processors raises the question for many users: how do you effectively calculate the real speed of a multi-core system? Is a 4-core 3Ghz system really 12Ghz? Read on as we investigate. Today’s Question & Answer session comes to us courtesy of SuperUser—a subdivision of Stack Exchange, a community-drive grouping of Q&A web sites. 6 Start Menu Replacements for Windows 8 What Is the Purpose of the “Do Not Cover This Hole” Hole on Hard Drives? How To Log Into The Desktop, Add a Start Menu, and Disable Hot Corners in Windows 8

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  • runt integrated intel graphics card + nvidia pcie graphics card?

    - by Roberto
    Its days I am searching for information/help. Is this possible at all? I am running Ubuntu 11.10 on an intel core i3 530 on a intel dh55hc mainboard. I have 2 monitors attached, one on dvi and one on hdmi. I want to ad a third or eaven a fourth monitor using an additional graphics card nvidia in pcie slot. I cant get an image on all monitors at the same time. I am wondering if this is possible at all? Any ideas where I can get information about this? Thanks in advance Roberto

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  • Windows 8 ne serait pas encore finalisé pour le patron d'Intel, qui estime que des améliorations sont encore nécessaires

    Windows 8 ne serait pas encore finalisé pour le patron d'Intel qui estime que des améliorations sont encore nécessaires Microsoft va officiellement lancer Windows 8 le 26 octobre avec une nouvelle génération de tablettes et PC fonctionnant sous le système d'exploitation. Mais, il semblerait que l'OS ne soit pas encore totalement finalisé. C'est en tout cas ce que pense Paul Otellini, le PDG d'Intel, selon un article Bloomberg. Le patron du constructeur de microprocesseurs qui est le partenaire le plus proche de Microsoft aurait déclaré lors d'une réunion privée avec son équipe de Taïwan que Windows 8 va être lancé avant d'être finalisé. D'un point de vu comm...

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  • AMD : des puces à trois et quatre coeurs pour PC portables et une baisse des prix pour contrer Intel

    Mise à jour du 12/05/10 AMD : des puces à trois et quatre coeurs pour portables Et une baisse des prix pour contrer Intel AMD vient de dévoiler des puces triple-coeurs et quadri-coeurs spécialement destinés au marché des Notebooks. Ces puces Phenom II tourneront à une vitesse allant entre 1.6GHz et 2.3GHz. Elles visent bien évidemment à essayer de contrer la concurrence de plus en plus virulente d'Intel qui devrait, de son coté, lancer une gamme de puces entre ses Atoms (pour Netbooks) et ses Core i5/i3 (pour desktop) spécialement conçues pour ce marché des portables hybrides. Rappelons que les Notebooks ...

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  • Which drivers do I need for Ethernet and CAN bus on Intel Tolapai?

    - by Hanno Fietz
    I've installed 10.04 Server on an embedded machine (NISE 110 by Nexcom) and the builtin Ethernet and CAN-bus controllers don't work out of the box. The controller seems to be an Intel EP80579 chipset for both, according to lspci. I tried Intel's product website, where they seem to have FreeBSD drivers only. There's also drivers for RedHat, but I'm struggling with the manual build required to get them to work. Googling so far didn't get me anywhere. Which drivers do I need, and where do I get them?

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  • Les premières puces Sandy Bridge corrigées ont été livrées, la rapidité d'Intel rassure les constructeurs de cartes mère

    Les premières puces Sandy Bridge corrigées ont été livrées, la rapidité d'Intel rassure les constructeurs de cartes mère Mise à jour du 21.02.2011 par Katleen Intel semble avoir tenu ses engagements, à savoir livrer ses nouveau chipset (en remplacement des défectueux) à la fin février. Le second mois de l'année touche à sa fin et les premières puces de ce type viendraient d'être livrées. Le constructeur MSI a en effet déclaré en avoir reçu la première fournée, et s'atteler dès à présente à la réparation et au remplacement des cartes mères défectueuses concernées par le rappel. Les composants ainsi mis à jour porteront une étiquette indiquant "MSI B3 Stepping Ready...

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