I'm trying to create a generic build template for my Makefiles, kind of like they discuss in the eval documentation.

I can't seem to get the wildcard function to work within an eval. The basic code I'm having issues with looks like this.

SRC_DIR = ./src/

PROG_NAME = test

define PROGRAM_template
  $(1)_SRC_DIR = $(join $(SRC_DIR), $(1)/)
  $(1)_SRC_FILES = $(wildcard $$($(1)_SRC_DIR)*.c)
endef

$(eval $(call PROGRAM_template, $(PROG_NAME)))

all:
    @echo $(test_SRC_DIR)
    @echo $(test_SRC_FILES)
    @echo $(wildcard $(wildcard $(test_SRC_DIR)*.c)

When I run make with this, the output is

./src/test

[correct list of all .c files in ./src/test/]

Basically, the wildcard call within PROGRAM_template is not being eval'd as I expect it. The call results in an empty list.
The join call is being eval'd correctly though.

So, what am I doing wrong? My guess is that

$$($(1)_SRC_DIR) 

is not correct, but I can't figure out the right way to do it.

EDIT Once this was solved, it didn't take long for me to hit another issue with eval. I posted it as a new question at http://stackoverflow.com/questions/2428506/workaround-for-gnu-make-3-80-eval-bug