MakeFiles and dependencies
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by Michael
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Published on 2010-03-20T16:46:13Z
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2010/03/20
17:41 UTC
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makefile
Hello, I'm writing a makefile and I can't figure out how to include all my source files without having to write all source file I want to use. Here is the makefile I'm currently using:
GCC = $(GNUARM_HOME)\bin\arm-elf-gcc.exe
SOURCES=ShapeApp.cpp Square.cpp Circle.cpp Shape.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello
all: $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
#$(CC) $(LDFLAGS) $(OBJECTS) -o $@
.cpp.o:
$(GCC) -c $< -o $@
How do I automatically add new source file without having to add it to the sources line?
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