How to include clean target in makefile

Posted by neversaint on Stack Overflow See other posts from Stack Overflow or by neversaint
Published on 2010-04-14T07:01:47Z Indexed on 2010/04/14 7:13 UTC
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c

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c++

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unix

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linux

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makefile

I have a makefile that looks like this

CXX = g++ -O2 -Wall

all: code1 code2

code1: code1.cc utilities.cc
   $(CXX) $^ -o $@

code2: code2.cc utilities.cc
   $(CXX) $^ -o $@

What I want to do next is to include 'clean target' so that every time I run 'make' it will automatically delete the existing binary files of code1 and code2 before creating the new ones.

I tried to put these lines at the very end of the makefile, but it doesn't work

clean: 
    rm -f $@
    echo Clean done

What's the right way to do it?

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Developer IT

How to include clean target in makefile - Developer IT

How to include clean target in makefile

c

c++

unix

linux

makefile

Related posts about c

Related posts about c++

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The Definitive C++ Book Guide and List

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