I have the following GNU makefile:

.PHONY a b c d

a: b c
b: d
c: d
d:
    echo HI

I would like the target 'd' to be run twice -- since it is specified as a dependency by both b & c. Unfortunately, the target 'd' will be executed only once. The output of running make will simply be 'HI', instead of 'HI HI'.

How can I fix this?

Thanks!

To Clarify, the goal is something like this:

subdirs =  a b c

build: x y

x: target=build
x: $(subdirs)

y: target=prepare
y: $(subdirs)

$(subdirs):
    $(make) -f $@/makefile $(target)