Cache consistency & spawning a thread

Posted by Dave Keck on Stack Overflow See other posts from Stack Overflow or by Dave Keck
Published on 2010-06-06T14:15:43Z Indexed on 2010/06/06 14:22 UTC
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Background

I've been reading through various books and articles to learn about processor caches, cache consistency, and memory barriers in the context of concurrent execution. So far though, I have been unable to determine whether a common coding practice of mine is safe in the strictest sense.

Assumptions

  1. The following pseudo-code is executed on a two-processor machine:

    int sharedVar = 0;
    
    
    myThread()
    {
        print(sharedVar);
    }
    
    
    main()
    {
        sharedVar = 1;
        spawnThread(myThread);
        sleep(-1);
    }
    
  2. main() executes on processor 1 (P1), while myThread() executes on P2.

  3. Initially, sharedVar exists in the caches of both P1 and P2 with the initial value of 0 (due to some "warm-up code" that isn't shown above.)

Question

Strictly speaking – preferably without assuming any particular CPU – is myThread() guaranteed to print 1?

With my newfound knowledge of processor caches, it seems entirely possible that at the time of the print() statement, P2 may not have received the invalidation request for sharedVar caused by P1's assignment in main(). Therefore, it seems possible that myThread() could print 0.

References

These are the related articles and books I've been reading. (It wouldn't allow me to format these as links because I'm a new user - sorry.)

  1. Shared Memory Consistency Models: A Tutorial

    hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf

  2. Memory Barriers: a Hardware View for Software Hackers

    rdrop.com/users/paulmck/scalability/paper/whymb.2009.04.05a.pdf

  3. Linux Kernel Memory Barriers

    kernel.org/doc/Documentation/memory-barriers.txt

  4. Computer Architecture: A Quantitative Approach

    amazon.com/Computer-Architecture-Quantitative-Approach-4th/dp/0123704901/ref=dp_ob_title_bk

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