I am trying to create a makefile that automatically compiles and links my .cpp files into an executable via .o files. What I can't get working is automated (or even manual) dependency generation. When i uncomment the below commented code, nothing is recompiled when i run make build. All i get is make: Nothing to be done for 'build'., even if x.h (or any .h file) has changed. I've been trying to learn from this question: Makefile, header dependencies, dmckee's answer, especially. Why isn't this makefile working?

Clarification: I can compile everything, but when I modify any header file, the .cpp files that depend on it aren't updated. So, if I for instance compile my entire source, then I change a #define in the header file, and then run make build, and I get Nothing to be done for 'build'. (when I have uncommented either commented chunks of the below code).

CC=gcc
CFLAGS=-O2 -Wall
LDFLAGS=-lSDL -lstdc++
SOURCES=$(wildcard *.cpp)
OBJECTS=$(patsubst %.cpp, obj/%.o,$(SOURCES))
TARGET=bin/test.bin

# Nothing happens when i uncomment the following. (automated attempt)
#depend: .depend
#
#.depend: $(SOURCES)
#   rm -f ./.depend
#   $(CC) $(CFLAGS) -MM $^ >> ./.depend;
#
#include .depend

# And nothing happens when i uncomment the following. x.cpp and x.h are files in my project. (manual attempt)
#x.o: x.cpp x.h


clean:
    rm -f $(TARGET)
    rm -f $(OBJECTS)

run: build
    ./$(TARGET)

debug: build
    nm $(TARGET)
    gdb $(TARGET)

build: $(TARGET)

$(TARGET): $(OBJECTS)
    @mkdir -p $(@D)
    $(CC) $(LDFLAGS) $(OBJECTS) -o $@

obj/%.o: %.cpp
    @mkdir -p $(@D)
    $(CC) -c $(CFLAGS) $< -o $@

include $(DEPENDENCIES)