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  • NIC interface names in /proc/interrupts

    - by Gallus
    When I look at /proc/interrupts: $ cat /proc/interrupts CPU0 CPU1 (...) 12: 4 0 IO-APIC-edge i8042 14: 145 65310875 IO-APIC-edge ide0 50: 0 0 IO-APIC-level uhci_hcd:usb5, Intel ICH7 58: 5388 7983508 IO-APIC-level libata 169: 812427252 1236572641 IO-APIC-level skge, eth1 217: 6 0 IO-APIC-level ehci_hcd:usb1, uhci_hcd:usb2 225: 0 0 IO-APIC-level uhci_hcd:usb3 233: 60 3108720778 IO-APIC-level uhci_hcd:usb4, skge I can see two skge and one eth1 entries. All of them are the network cards. Because of the general name "skge" (which is the name of the network driver of the card) I can't easily reocognize, which NIC occupies which interrupt. How to make linux use more descriptive names in the entries? Or: Is there any alternative way to obtain INT information instead of /proc/interrupt? My final goal is to manipulate smp_affinities of the NICs.

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  • Distribute IP packets accross different NIC queues with MSI (Message Signalled Interrupts)

    - by Ansis Atteka
    NetXtreme II BCM5709 Gigabit Ethernet NIC supports MSI feature (Message Signaled Interrupts) and it has 8 queues. Each queue has its own Interrupt handler in /proc/interrupts. What I am trying to accomplish is to tell NIC which packets should go to which queue. Questions: Is it possible to manually specify which IP packets should go to which queue by encapsulated protocol type (e.g. IPsec packets go in one queue, while TCP packets go in another queue)? If it is possible - how can I do it under Linux? If it is not possible - should I look at MSI-X capable NIC cards to solve this problem? More details: We have one Interface that is terminating IPSec and forwarding/terminating TCP connections. The IPSec packet decryption is inlined (this means that decryption is done under the same ksoftirqd/X context). We are trying to find out if we will be able to improve total performance if IPSec packets will be scheduled on another CPU than TCP packets. One more limitation is that IPSec code is not MP-safe, hence I can not run it under more than one ksoftirqd/X. By default it seems that packets are distributed/hashed by source IP over the 8 NIC queues. The bottleneck is IPSec that chokes out TCP traffic while it is decrypting/encrypting IPSec packets at ~100% CPU. OS is Ubuntu 10.10 (2.6.32-27-server) and NIC is Broadcom BCM5709.

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  • BIOS interrupts, privilege levels and paging

    - by Jack
    Hi, I was learning about Intel 8086-80486 CPUs and their interactions with HW. But I still don´t understand it quite well. Please, help me fill blank spots. First, I know that CPU communicates with HW using BIOS interrupts. But, what really happens in PC, when I call some INT instruction? I know that according the interrupt table some instructions begin to execute, but how by executing some instructions can BIOS recognize what I want to do? Becouse as far as I know, CPU has no extra communication channel with BIOS, it can only adress memory and receive data. So how can I instruct BIOS to do something, when I can only address RAM? Next thing I don't understand is about privilege levels. I know about ring model, and access rights, but how does the CPU know which privilege level has executed an instruction? I think that these privileges apply only when intruction is trying to address memory, but how does an application get its privilege level? I mean I know its level 3, but how is it set? And last thing, I know that paging is address scheme that is used to support aplication-transparent virtual memory, or swapping, but I could not find any information about how paging is tied with protected mode. Like if paging is like next mode independent of protected mode, or its somehow implemented within protected mode. And if it is implemented in protected mode, isn´t it too slow, to first address application space, then offset, and then paging folder, page and offset once again?

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  • BIOS interrupts, priviledge levels and paging

    - by Jack
    Hi, I was learning about Intel 8086-80486 CPUs and their interactions with HW. But I still don´t understand it quite well. Please, help me fill blank spots. First, I know that CPU communicates with HW using BIOS interrupts. But, what really happens in PC, when I call some INT instruction? I know that according the interrupt table some instructions begin to execute, but how by executing some instructions can BIOS recognize what I want to do? Becouse as far as I know, CPU has no extra communication channel with BIOS, it can only adress memory and receive data. So how can I instruct BIOS to do something, when I can only adress RAM? Next thing I dont understand is about priviledge levels. I know about ring model, and acess rights, but how CPU knows which priviledge level has executed instruction? I think that these priviledges apply only when intruction is trying to adress memory, but how applications gets its priviledge level? I mean I know its level 3, but how its set? And last thing, I know that paging is adress scheme that is used to support aplication-transparent virtual memory, or swaping, but I could not find any informations about how is paging tied with protected mode. Like if paging is like next mode independent of protectet mode, or its somehow implemented within protected mode. And if it is implemented in protected mode, isn´t it too slow, to first adress application space, than offset, and than paging folder, page and offset once again? Thank you for every response.

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  • Micro sound breaks/interrupts on Windows 7

    - by cand
    Hello all, I've been experiencing strange behavior recently. When listening to mp3 or watching movie or whatever that uses sound, I get micro breaks in sound. It's like it hangs or cuts a fragment for about 0.5s. When I start OS, it's ok, but as time passes it gets worse, to the extent that music is unlistenable being interrupted every 2 seconds. I haven't found any relevance between this behavior and hardware usage, I don't think it's directly related to HDD (or it might be but with significant delay). I have updated soundcard drivers and it didn't help a lot. My system is Windows 7, computer is simple HP laptop, nx7300-Ru374ES with WD Caviar Scorpio Blue hard drive inside and integrated soundcard on it (I can check the model later if it's important). Did anybody encounter such problem ? Maybe it's a common thing on Windows 7 or someone knows how to solve it? Thanks in advance.

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  • ACPI 30k+ interrupts per second

    - by ultimatebuster
    My computer is currently doing something like 30k+ interrupts per second. This causes battery issues as well as the CPU being always stuck at the highest speed, making it very hot (overheating.. 75C at IDLE) Powertop info: 99.4% (32052.4) [acpi] <interrupt> 0.3% (115.9) [iwlagn] <interrupt> Just to clarify this started suddenly a couple of days ago. It didn't have this issue before (though I had a tonne of headaches with Linux on my computer in general..)

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  • Exceptions & Interrupts

    - by Betamoo
    When I was searching for a distinction between Exceptions and Interrupts, I found this question Interrupts and exceptions on SO... Some answers there were not suitable (at least for assembly level): "Exception are software-version of an interrupt" But there exist software interrupts!! "Interrupts are asynchronous but exceptions are synchronous" Is that right? "Interrupts occur regularly" "Interrupts are hardware implemented trap, exceptions are software implemented" Same as above! I need to find if some of these answers were right , also I would be grateful if anyone could provide a better answer... Thanks!

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  • Which Cortex-M3 interrupts can I use for general purpose work?

    - by Captain NedD
    I'd have some code that needs to be run as the result of a particular interrupt going off. I don't want to execute it in the context of the interrupt itself but I also don't want it to execute in thread mode. I would like to run it at a priority that's lower than the high level interrupt that precipitated its running but also a priority that higher than thread level (and some other interrupts as well). I think I need to use one of the other interrupt handlers. Which ones are the best to use and what the best way to invoke them? At the moment I'm planning on just using the interrupt handlers for some peripherals that I'm not using and invoking them by setting bits directly through the NVIC but I was hoping there's a better, more official way. Thanks,

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  • CPU Usage at 100% with "Hardware Interrupts"

    - by eventualEntropy
    After turning on my desktop one day, I found that my CPU usage was maxed out at 100%, with 99% of that going to hardware "Interrupts". I tried to enable/disable all my devices one by one through the device manager, and found that I could get the CPU usage used by the Interrupts down to 50% by disabling all devices labelled "USB Host Controller" (except the ones for the mouse/keyboard). I found that I also got 10-20% more from disabling "High Definition Audio Controller". Following the tutorial at: http://www.msfn.org/board/topic/140263-how-to-get-the-cause-of-high-cpu-usage-by-dpc-interrupt/ Led me to similar conclusions (that is, that the culprit is mostly "USB Host Controller"): I've tried updating my asus motherboard driver and my video card driver. This is on Windows 7 64 bit. I've spent hours trying to figure this out and I'm running out of ideas short of formatting (which might still not fix it!).

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  • How to use Timer broadcast on Multi-Processor system with linux 3.10?

    - by kevin.ji
    Hardware: ARM Cortex-A9 * 2 Software: linux-3.10.0 The platform has 2 cores of arm cortex-a9. Item CONFIG_LOCAL_TIMERS is not set in linux menuconfig. I want to use only one hardware timer to supply tick for all cpu. Interrupts looks like: CPU0 CPU1 57: 6697 0 GIC timer 81: 213 0 GIC uart-pl011 103: 0 0 GIC gmac0 104: 0 0 GIC gmac1 IPI0: 0 1 CPU wakeup interrupts IPI1: 0 0 Timer broadcast interrupts IPI2: 967 866 Rescheduling interrupts IPI3: 0 0 Function call interrupts IPI4: 1 2 Single function call interrupts IPI5: 0 0 CPU stop interrupts IPI6: 0 0 CPU backtrace Err: 0 Timer broadcast interrupts counter does not add. And it looks like that cpu1 does not work at all.But this method works well with linux-3.4, and the interrupt info looks as below in linux-3.4: # cat /proc/interrupts CPU0 CPU1 57: 8596 0 GIC timer 81: 91 0 GIC uart-pl011 103: 0 0 GIC gmac0 104: 0 0 GIC gmac1 IPI0: 0 8560 Timer broadcast interrupts IPI1: 884 1020 Rescheduling interrupts IPI2: 0 0 Function call interrupts IPI3: 0 6 Single function call interrupts IPI4: 0 0 CPU stop interrupts IPI5: 0 0 CPU backtrace Err: 0 The count of Timer broadcast interrupts is adding. And all of cpus work well. I don't know why. Any answer is welcome. :)

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  • How are interrupts handled by dual processor machines?

    - by jeffD
    I have an idea of how interrupts are handled by a dual core CPU. I was wondering about how interrupt handling is implemented on a board with more than one physical processor. Is any of the interrupt responsibility determined by the physical board's configuration? Each processor must be able to handle some types of interrupts, like disk I/O. Unless there is some circuitry to manage and dispatch interrupts to the appropriate processor? My guess is that the scheme must be processor neutral, so that any processor and core can run the interrupt handler. If a core is waiting on a disk read, will that core be the one to run the interrupt handler when the disk is ready?

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  • Multithreading and Interrupts

    - by Nicholas Flynt
    I'm doing some work on the input buffers for my kernel, and I had some questions. On Dual Core machines, I know that more than one "process" can be running simultaneously. What I don't know is how the OS and the individual programs work to protect collisions in data. There are two things I'd like to know on this topic: (1) Where do interrupts occur? Are they guaranteed to occur on one core and not the other, and could this be used to make sure that real-time operations on one core were not interrupted by, say, file IO which could be handled on the other core? (I'd logically assume that the interrupts would happen on the 1st core, but is that always true, and how would you tell? Or perhaps does each core have its own settings for interrupts? Wouldn't that lead to a scenario where each core could react simultaneously to the same interrupt, possibly in different ways?) (2) How does the dual core processor handle opcode memory collision? If one core is reading an address in memory at exactly the same time that another core is writing to that same address in memory, what happens? Is an exception thrown, or is a value read? (I'd assume the write would work either way.) If a value is read, is it guaranteed to be either the old or new value at the time of the collision? I understand that programs should ideally be written to avoid these kinds of complications, but the OS certainly can't expect that, and will need to be able to handle such events without choking on itself.

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  • kernel software trap handling

    - by Tony
    I'm reading a book on Windows Internals and there's something I don't understand: "The kernel handles software interrupts either as part of hardware interrupt handling or synchronously when a thread invokes kernel functions related to the software interrupt." So does this mean that software interrupts or exceptions will only be handled under these conditions: a. When the kernel is executing a function from said thread related to the software exception(trap) b. when it is already handling a hardware trap Is my understanding of this correct? The next bit: "In most cases, the kernel installs front-end trap handling functions that perform general trap handling tasks before and after transferring control to other functions that field the trap." I don't quite understand what it means by 'front-end trap handling functions' and 'field the trap'? Can anyone help me?

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  • Who interrupts my thread?

    - by Thirler
    I understand what an InterruptedException does and why it is thrown. However in my application I get it when waiting for SwingUtilities.invokeAndWait() on a thread that is only known by my application, and my application never class Thread.interrupt() on any thread, also it never passes the reference of the thread on to anyone. So my question is: Who interrupts my thread? Is there any way to tell? Is there a reason why the InterruptedException doesn't contain the name of the Thread that requests the interrupt? I read that it could be a framework or library that does this, we use the following, but I can't think of reason for them to interrupt my thread: Hibernate Spring Log4J Mysql connector

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  • What can cause peaks in pagetables in /proc/meminfo ?

    - by Fuzzy76
    I have a gameserver running Debian Lenny on a VPS host. Even when experiencing a fairly low load, the players start experiencing major lag (ping times rise from 50 ms to 150-500 ms) in bursts of 3 - 10 seconds. I have installed Munin server monitoring, but when looking at the graphs it looks like the server has plenty of CPU, RAM and bandwidth available. The only weird thing I noticed is some peaks in the memory graph attributed to "page_tables" which maps to PageTables in /proc/meminfo but I can't find any good information on what this might mean. Any ideas what might be causing this? If you need any more graps, just let me know. The interrupts/second count is at roughly 400-600 during this period (nearly all from eth0). The drop in committed was caused by me trying to lower the allocated memory for the server from 512MB to 256MB, but that didn't seem to help.

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  • How does an OS communicate with other hardware components?

    - by Jack
    How can a program running on a CPU (mostly OS) access other PC hardware? Such as Graphic card, HDD and so? From what I read, in DOS, this was done using BIOS calls, specifically the INT instruction. But, the INT instruction should only jump to the certain space in RAM. So how can some program stored in RAM access other computer hardware, when the CPU can only access RAM, and receive interrupts? Does Windows use INT instructions as well, or is there a new way to communicate with the hardware?

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  • What's the difference between hardware and software interrupt?

    - by robotrobert
    I'm gonna sketch my understanding of both. I've googled around but i'm not sure about my knowledge. Please correct me! Hardware interrupt is generated by the operation system event scheduler to reassign the cpu time for another process. Is this true? Software interrupt can be generated from a running program who wants for example to read a file, and for that we need to reassign the cpu for the appropriate operation system call. Is this true? Is there other kind of software/hardware interrupts?

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  • How computers display raw, low-level text and graphics

    - by panic
    My ever-growing interest in computers is making me ask deeper questions, that we don't seem to have to ask anymore. Our computers, at boot, as far as I understand it, are in text mode, in which a character can be displayed using the software interrupt 0x10 when AH=0x0e. We've all seen the famous booting font that always looks the same, regardless of what computer is booting. So, how on earth do computers output graphics at the lowest level, say, below the OS? And also, surely graphics aren't outputted a pixel at a time using software interrupts, as that sounds very slow? Is there a standard that defines basic outputting of vertices, polygons, fonts, etc. (below OpenGL for example, which OpenGL might use)? What makes me ask is why OS' can often be fine without official drivers installed; how do they do that? Apologies if my assumptions are incorrect. I would be very grateful for elaboration on these topics!

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  • Excel COM Add-In dialog interrupts script

    - by usac
    Hi all! I have written an Excel COM Add-In in C++ for automation of Excel with VBA. It contains an own dialog showing some general informations about the Add-In. Now i create a button in Excel that opens the dialog. Leaving the dialog with the escape key leads to an Excel message that the script is being interrupted instead of just closing the dialog. I could suppress the interruption message with: Application.EnableCancelKey = xlDisabled But that seems not to be the solution as the script can not be interrupted any more. Here is an example how i use VBA to open the dialog: Private Sub ShowAboutDialog_Click() Dim oComAddIn As COMAddIn Set oComAddIn = Application.COMAddIns.Item("MyComAddIn.Example") oComAddIn.Connect = True Call oComAddIn.Object.ShowAboutDlg End Sub My guess is that the problem is somewhere in the message handler of the dialog: INT_PTR CALLBACK CAboutDialog::AboutDlg( HWND hwndDlg, UINT uMsg, WPARAM wParam, LPARAM lParam) { switch(uMsg) { ... case WM_COMMAND: if (LOWORD(wParam) == IDOK || LOWORD(wParam) == IDCANCEL) { // Here, the ESCAPE key should also be trapped? EndDialog(hwndDlg, LOWORD(wParam)); return TRUE; } ... } return FALSE; } The Dialog is created with: DialogBox(g_hModule, MAKEINTRESOURCE(IDD_ABOUT), hWndParent, (DLGPROC)AboutDlg) Thanks a lot!

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  • ExecutorService that interrupts tasks after a timeout

    - by scompt.com
    I'm looking for an ExecutorService implementation that can be provided with a timeout. Tasks that are submitted to the ExecutorService are interrupted if they take longer than the timeout to run. Implementing such a beast isn't such a difficult task, but I'm wondering if anybody knows of an existing implementation.

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  • How CPU finds ISR and distinguishes between devices

    - by ripunjay-tripathi-gmail-com
    I should first share all what I know - and that is complete chaos. There are several different questions on the topic, so please don't get irritated :). 1) To find an ISR, CPU is provided with a interrupt number. In x86 machines (286/386 and above) there is a IVT with ISRs in it; each entry of 4 bytes in size. So we need to multiply interrupt number by 4 to find the ISR. So first bunch of questions is - I am completely confused in mechanism of CPU receiving the interrupt. To raise an interrupt, firstly device shall probe for IRQ - then what ? The interrupt number travels "on IRQ" towards CPU? I also read something like device putting ISR address on data bus ; whats that then ? What is the concept of devices overriding the ISR. Can somebody tell me few example devices where CPU polls for interrupts? And where does it finds ISR for them ? 2) If two devices share an IRQ (which is very much possible), how does CPU differs amongst them ? What if both devices raise an interrupt of same priority simultaneously. I got to know there will be masking of same type and low priority interrupts - but how this communication happens between CPU and device controller? I studied the role of PIC and APIC for this problem, but could not understand. Thanks for reading. Thank you very much for answering.

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