How to declare and use 1D and 2D byte arrays in Verilog?
- by loveblessings
How to declare and use 1D and 2D byte arrays in Verilog?
eg. how to do something like
byte a_2D[3][3];
byte a_1D[3];
// using 1D
for (int i=0; i< 3; i++)
{
a_1D[i] = (byte)i;
}
// using 2D
for (int i=0; i< 3; i++)
{
for (int j=0; j< 3; j++)
{
a_2D[i][j] = (byte)i*j;
}
}
