How to declare and use 1D and 2D byte arrays in Verilog?

Posted by loveblessings on Stack Overflow See other posts from Stack Overflow or by loveblessings
Published on 2010-06-10T03:46:24Z Indexed on 2010/06/10 3:52 UTC
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byte a_2D[3][3];
byte a_1D[3];

// using 1D
for (int i=0; i< 3; i++)
{
    a_1D[i] = (byte)i;
}

// using 2D
for (int i=0; i< 3; i++)
{
    for (int j=0; j< 3; j++)
    {
        a_2D[i][j] = (byte)i*j;
 }
}

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