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  • Virtual Machine Performance - More RAM or More Processor?

    - by webworm
    When looking to improve Virtual Machine performance what would be better ... Increasing the available RAM or increasing the processor power? Here is my choice ... Core 2 Duo @ 2.4 GHz with 8 GB RAM and integrated graphics (Mac Book Pro 13") Core i7 @ 2.6 GHz with 4 GB RAM and 512 MB dedicated graphics (Mac Book Pro 15") I plan to run Windows x64 in the VM with SQL Server 2008, Visual Studio 2010, and SharePoint 2010. I am planning to run VMWare Fusion v3. I also didn't know if a dedicated graphics card makes a difference when using a Virtual Machine. Thank you.

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  • Dell Dimension 2350 with a Pentium IV processor and integrated video and network chips running Fedor

    - by Jim Dobbs
    Dell Dimension 2350 with a Pentium IV processor and integrated video and network chips running Fedora12 does a "Sleeping Beauty" and I, apparently, am not am not a "handsome prince"! The system puts video and network to sleep and it will not wakeup. I have heard of this problem on laptops, but this is a tower. Any ideas or help is appreciated. I tried to ping the network card from another system and ping fails. The logs indicate that the system continues to be active. Pressing keyboard short-cut keys makes the disk light blink but neither the video or network card comes alive. Failing all else, are there any Linux commands that I could schedule in cron to pulse video and network adapters hourly that will keep them awake? Or, should I wait on Fedora13? Before this machine, I built a Dimension 2400 with Pentium IV and it had the same problem. Fedora9 on the same hardware is fine.

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  • How do I overclock a dual core processor?

    - by Pankaj Bhardwaj
    This is a serious problem. I want to speed up my compilation process. I have never been especially fond of overclocking, however my current compilation time for my project makes my crazy! I found information about which parameters I should change to overclock and which values are safe. However, I have one basic problem. I don't have the ability to change this option in my BIOS. It is possible that these options have been blocked by the system administrators? Getting a faster processor is not an option. How do I edit the proper values to overclock my CPU. Do I need to flash my bios to another version? My specs: Entium Dual-Core Cpu E5400 @2.7GHz Asrock motherboard 4GB RAM Windows 7 Ultimate 32-bit

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  • VirtualBox VM settings between different CPUs (Processor/Acceleration)

    - by Level1Coder
    I have 2 PCs, 1 with a INTEL-Q9550 (YES-VT-x) and another with INTEL-E2160 (NO-VT-x) I will be using the Q9550 first to create a new VM, install XP and install stuff I'll need. Once this VM is golden, I plan on migrating this VM over to the E2160 machine. The question is, while creating/preparing this VM on the Q9550, should I disable all the following settings below to make sure the E2160 can start this VM without errors? Q9550 Default VM Settings ========================= PROCESSOR [X] Enable PAE/NX ACCELERATION [X] Enable VT-x/AMD-V [X] Enable Nested Paging

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  • What motherboard for a Core i7 920 Processor?

    - by jasondavis
    I am wanting to build a really nice PC, price is not to important as I will buy pieces every week or whatever it takes until I get everything I need. I am not a gamer but I would like to watch video and have 3-4 monitors. I do a lot of programming and use a lot of big programs so I would like to go all out and get a lot of Memory, probably at least 12gb but possibly more even as I see many boards support up to 24gb now. Will be using Windows 7. I have decided to go with the Core i7 920 Processor BX80601920. Based on what I posted above, can you please recommend some good motherboards I should look at ? Also some good places to purchase them online. Thanks for any help, tips, etc.

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  • recommendation for configuration for a multi-core guestOS

    - by reidLinden
    Hi there, I've just received an upgraded Host machine, and am looking to push some of those advances to my workstations Guest OS(s). In particular, I used to have a single processor, with 2 cores, so my guestOS only had 1/1. Now, I've got a single processor with 8 cores, so I'm curious about what would be recommended for my GuestOS now? 1 processor/4 cores? 2 processors/2Cores? 4 processors/1 core? My instinct says to stick with the number of physical processors (or less), but, is that based on reality? I spent a good while looking for an answer to this, but perhaps my google-karma isn't in my favor today. Suggestions?

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  • Multiple SQL Standard Instances on 4 Processor/32-core Server

    - by Theowood
    We have a large 4 processor/32-core server with 192GB of memory available in the data center and over twenty small SQL Standard databases to consolidate. They are a mix of SQL 2012 and 2008 R2 for 3rd-party apps. Is there any issue with simply installing two instances of SQL Standard on the server - one for 2012 and one for 2008 R2 ? Each instance will use up to 64GB out of the 192GB and 16 cores. If we did this with Enterprise, the licensing would be a fortune and the Enterprise features are not needed.

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  • Can a processor upgrade cause BSOD?

    - by Daniel
    I Had the following hardware setup: Phenom II X4 945 Asus M4A97 4GB DDR2 OCZ Radeon HD5850 OCZ Agility 2 120 GB Windows 7 x64 Pro Fully updated (latest drivers and windows update patches) Then I bought an used Phenom II X6 1090T and installed it without formatting. Since that my computer started BSODing almost every time I'm playing any game and with different error messages, like: page fault in non-paged area bad pool header the video memory manager found a problem error in dxgmm1.sys(or something like that) And when it doesn't BSOD the game simply crashes. I have tried: Updating BIOS Reseting BIOS to defaults Reinstalling Video Drivers Installing the latest DirectX All that's left is to do a full format and I don't want to do that since it's going to be a lot of work to fine tune windows to my preferences again. So is my "new" processor defective or do I really need to format the computer? Update: I use a (properly installed) custom cooler from Coolermaster and both the BIOS and the Open Hardware Monitor(Application) attest the CPU is not overheating, so I guess the CPU its defective and since I bought it from a guy over the Internet I'm probably screwed

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  • Will Windows repair my multi-boot when I format the 1st physical partition with boot sector?

    - by user2353806
    Due to historical reasons I got a laptop with Vista, Windows 7 and Windows Server 2008R2 partitions. (boot from external wasn´t that viable) Nothing (Windows Repair, bootrec /whateveroption) worked when I restored only the Windows 7 and WS2k8 with Acronis TrueImage. Don´t ask me through what idiotic error messages I went during repair tries. (Wrong Windows version,...) So I grudgingly restored all three - with the little additional excursion that I thought changing the active partition to the Windows 7 partition would move the boot sector and let me format the Vista part... Oh no. Seems too logical for MS. (Dunno what I changed, but today it will let me format!) So the real question is: Will formatting the Vista part trash things again beyond comprehension or will Windows Repair bring back the boot rec and remove Vista from the boot options? Or should I just erase all the files to avoid trashing the boot? Where will the boot rec be (after repair) when I format the Vista? On 1st or 2nd partition? And if I get drunk and install Windows 8.1 on the 1st, will anything work? ;-) Thanks

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  • How to chain GRUB2 for Ubuntu 10.04 from Truecrypt & its bootloader (multi boot alongside Windows XP partition)?

    - by Rob
    I want Truecrypt to ask for password for Windows XP as usual but with the standard [ESC] option, on selecting that, i.e via Escape key, I want it to find the grub for the (unencrypted) Ubuntu install. I've installed Windows XP on the 120Gb hard drive of a Toshiba NB100 netbook then partitioned to make room for Ubuntu 10.04 and installed that after the Windows XP install. When I encrypt Windows XP, Truecrypt will overwrite the grub entry in the master boot record (MBR), I believe (?) and I won't be able to choose between XP and Ubuntu anymore. So I need to restore it back. I've searched fairly extensively for answers on Ubuntu forums and elsewhere but have not yet found a complete answer that covers all eventualities, scenarios and error messages, or otherwise they talk of legacy GRUB and not GRUB2. Ubuntu 10.04 uses GRUB2. My setup: Partitions: Windows XP, NTFS (to be encrypted with Truecrypt), 40Gb /boot (Ext4, 1Gb) Ubuntu swap, 4Gb Ubuntu / (root) - main filesystem (20gb) NTFS share, 55Gb I know that the Truecrypt boot loader replaces the GRUB when boot up because I've already tried it on another laptop. I want boot loader screen to look something like the usual: Truecrypt Enter password: (or [ESC] to skip) password is for WindowsXP and on pressing [ESC] for it to find the Ubuntu grub to boot from Thanks in advance for your help. The key area of the problem is how to instruct Truecrypt when escape key is pressed, and how the Grub/Ubuntu can be made visible to the truecrypt bootloader to find it, when the esc key is pressed. Also knowing as chaining.

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  • NEC uPD720200 USB 3.0 not working on Ubuntu 12.04

    - by Jagged
    I've recently installed Ubuntu 12.04 64-bit on a HP Envy 15 1104tx. Most stuff appears to be working fine with the exception of the two USB3 ports (USB2 port works fine). I've read a lot of articles but so far have not been able to find a solution. I've tried adding 'pci=nomsi' to '/etc/default/grub' but this made no difference. Some articles suggest booting into Windows and upgrading the firmware on the uPD720200. Any body had any experience of this? Is there a way I can checked the firmware version of the NEC uPD720200 in Linux to see if there is an update available? Any help appreciated. uname -a: Linux HP-ENVY-15-1104tx 3.2.0-26-generic #41-Ubuntu SMP Thu Jun 14 17:49:24 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux lshw: hp-envy-15-1104tx description: Notebook product: HP ENVY 15 Notebook PC (WF591PA#ABG) vendor: Hewlett-Packard version: 0492110000241910001420000 serial: CNF0301C79 width: 64 bits capabilities: smbios-2.6 dmi-2.6 vsyscall32 configuration: boot=normal chassis=notebook family=103C_5335KV sku=WF591PA#ABG uuid=434E4630-3330-3143-3739-60EB6906688F *-core description: Motherboard product: 1522 vendor: Hewlett-Packard physical id: 0 version: 36.35 serial: CNF0301C79 slot: Base Board Chassis Location *-firmware description: BIOS vendor: Hewlett-Packard physical id: 0 version: F.2B date: 10/12/2010 size: 1MiB capacity: 1472KiB capabilities: pci upgrade shadowing cdboot bootselect edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb biosbootspecification *-memory description: System Memory physical id: 13 slot: System board or motherboard size: 16GiB *-bank:0 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 0 serial: E13C4316 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:1 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 1 serial: E03C3E16 slot: Bottom size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:2 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 2 serial: 672279CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-bank:3 description: SODIMM DDR3 Synchronous 1333 MHz (0.8 ns) product: 9905428-043.A00LF physical id: 3 serial: 652286CC slot: On Board size: 4GiB width: 64 bits clock: 1333MHz (0.8ns) *-cpu description: CPU product: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz vendor: Intel Corp. physical id: 1d bus info: cpu@0 version: Intel(R) Core(TM) i7 CPU Q 820 @ 1.73GHz slot: CPU size: 1199MHz capacity: 1199MHz width: 64 bits clock: 1066MHz capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 popcnt lahf_lm ida tpr_shadow vnmi flexpriority ept vpid cpufreq configuration: cores=4 enabledcores=4 threads=8 *-cache:0 description: L3 cache physical id: 1e slot: L3 Cache size: 8MiB capacity: 8MiB capabilities: synchronous internal write-through unified *-cache:1 description: L2 cache physical id: 20 slot: L2 Cache size: 256KiB capacity: 256KiB capabilities: synchronous internal write-through unified *-cache:2 description: L1 cache physical id: 21 slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through instruction *-cache description: L1 cache physical id: 1f slot: L1 Cache size: 32KiB capacity: 32KiB capabilities: synchronous internal write-through data *-pci:0 description: Host bridge product: Core Processor DMI vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 11 width: 32 bits clock: 33MHz *-pci:0 description: PCI bridge product: Core Processor PCI Express Root Port 1 vendor: Intel Corporation physical id: 3 bus info: pci@0000:00:03.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:4000(size=4096) memory:d4100000-d41fffff ioport:c0000000(size=268435456) *-display description: VGA compatible controller product: Broadway PRO [Mobility Radeon HD 5800 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0 bus info: pci@0000:01:00.0 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi vga_controller bus_master cap_list rom configuration: driver=fglrx_pci latency=0 resources: irq:58 memory:c0000000-cfffffff memory:d4100000-d411ffff ioport:4000(size=256) memory:d4140000-d415ffff *-multimedia description: Audio device product: Juniper HDMI Audio [Radeon HD 5700 Series] vendor: Hynix Semiconductor (Hyundai Electronics) physical id: 0.1 bus info: pci@0000:01:00.1 version: 00 width: 64 bits clock: 33MHz capabilities: pm pciexpress msi bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:56 memory:d4120000-d4123fff *-pci:1 description: PCI bridge product: Core Processor PCI Express Root Port 3 vendor: Intel Corporation physical id: 5 bus info: pci@0000:00:05.0 version: 11 width: 32 bits clock: 33MHz capabilities: pci msi pciexpress pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 memory:d4000000-d40fffff *-usb description: USB controller product: uPD720200 USB 3.0 Host Controller vendor: NEC Corporation physical id: 0 bus info: pci@0000:02:00.0 version: 03 width: 64 bits clock: 33MHz capabilities: pm msi msix pciexpress xhci bus_master cap_list configuration: driver=xhci_hcd latency=0 resources: irq:16 memory:d4000000-d4001fff *-generic:0 UNCLAIMED description: System peripheral product: Core Processor System Management Registers vendor: Intel Corporation physical id: 8 bus info: pci@0000:00:08.0 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:1 UNCLAIMED description: System peripheral product: Core Processor Semaphore and Scratchpad Registers vendor: Intel Corporation physical id: 8.1 bus info: pci@0000:00:08.1 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:2 UNCLAIMED description: System peripheral product: Core Processor System Control and Status Registers vendor: Intel Corporation physical id: 8.2 bus info: pci@0000:00:08.2 version: 11 width: 32 bits clock: 33MHz capabilities: pciexpress cap_list configuration: latency=0 *-generic:3 UNCLAIMED description: System peripheral product: Core Processor Miscellaneous Registers vendor: Intel Corporation physical id: 8.3 bus info: pci@0000:00:08.3 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:4 UNCLAIMED description: System peripheral product: Core Processor QPI Link vendor: Intel Corporation physical id: 10 bus info: pci@0000:00:10.0 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-generic:5 UNCLAIMED description: System peripheral product: Core Processor QPI Routing and Protocol Registers vendor: Intel Corporation physical id: 10.1 bus info: pci@0000:00:10.1 version: 11 width: 32 bits clock: 33MHz configuration: latency=0 *-multimedia description: Audio device product: 5 Series/3400 Series Chipset High Definition Audio vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 05 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:55 memory:d4200000-d4203fff *-pci:2 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:17 ioport:3000(size=4096) memory:d3000000-d3ffffff ioport:d0000000(size=16777216) *-network description: Wireless interface product: Centrino Advanced-N 6200 vendor: Intel Corporation physical id: 0 bus info: pci@0000:03:00.0 logical name: wlan0 version: 35 serial: 00:27:10:40:e4:68 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list ethernet physical wireless configuration: broadcast=yes driver=iwlwifi driverversion=3.2.0-26-generic firmware=9.221.4.1 build 25532 latency=0 link=no multicast=yes wireless=IEEE 802.11abgn resources: irq:54 memory:d3000000-d3001fff *-pci:3 description: PCI bridge product: 5 Series/3400 Series Chipset PCI Express Root Port 2 vendor: Intel Corporation physical id: 1c.1 bus info: pci@0000:00:1c.1 version: 05 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:16 ioport:2000(size=4096) memory:d2000000-d2ffffff ioport:d1000000(size=16777216) *-network description: Ethernet interface product: AR8131 Gigabit Ethernet vendor: Atheros Communications Inc. physical id: 0 bus info: pci@0000:04:00.0 logical name: eth0 version: c0 serial: 60:eb:69:06:68:8f size: 1Gbit/s capacity: 1Gbit/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress vpd bus_master cap_list ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=atl1c driverversion=1.0.1.0-NAPI duplex=full firmware=N/A ip=10.161.0.147 latency=0 link=yes multicast=yes port=twisted pair speed=1Gbit/s resources: irq:57 memory:d2000000-d203ffff ioport:2000(size=128) *-usb description: USB controller product: 5 Series/3400 Series Chipset USB2 Enhanced Host Controller vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 05 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:20 memory:d4205800-d4205bff *-pci:4 description: PCI bridge product: 82801 Mobile PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci@0000:00:1e.0 version: a5 width: 32 bits clock: 33MHz capabilities: pci subtractive_decode bus_master cap_list *-isa description: ISA bridge product: Mobile 5 Series Chipset LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 05 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: RAID bus controller product: 82801 Mobile SATA Controller [RAID mode] vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 logical name: scsi0 version: 05 width: 32 bits clock: 66MHz capabilities: storage msi pm bus_master cap_list emulated configuration: driver=ahci latency=0 resources: irq:45 ioport:5048(size=8) ioport:5054(size=4) ioport:5040(size=8) ioport:5050(size=4) ioport:5020(size=32) memory:d4205000-d42057ff *-disk description: ATA Disk product: OCZ-VERTEX3 physical id: 0.0.0 bus info: scsi@0:0.0.0 logical name: /dev/sda version: 2.15 serial: OCZ-0350P6H316X5KUQE size: 223GiB (240GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 signature=000592dd *-volume:0 description: EXT4 volume vendor: Linux physical id: 1 bus info: scsi@0:0.0.0,1 logical name: /dev/sda1 logical name: / version: 1.0 serial: e741f18c-cfc5-4bce-b1e7-f80e517a3a22 size: 207GiB capacity: 207GiB capabilities: primary bootable journaled extended_attributes large_files huge_files dir_nlink recover extents ext4 ext2 initialized configuration: created=2012-06-15 06:49:27 filesystem=ext4 lastmountpoint=/ modified=2012-06-14 21:23:42 mount.fstype=ext4 mount.options=rw,relatime,errors=remount-ro,user_xattr,barrier=1,data=ordered mounted=2012-07-10 16:18:20 state=mounted *-volume:1 description: Extended partition physical id: 2 bus info: scsi@0:0.0.0,2 logical name: /dev/sda2 size: 15GiB capacity: 15GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume description: Linux swap / Solaris partition physical id: 5 logical name: /dev/sda5 capacity: 15GiB capabilities: nofs *-serial UNCLAIMED description: SMBus product: 5 Series/3400 Series Chipset SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 05 width: 64 bits clock: 33MHz configuration: latency=0 resources: memory:d4205c00-d4205cff ioport:5000(size=32) *-pci:1 description: Host bridge product: Core Processor QuickPath Architecture Generic Non-Core Registers vendor: Intel Corporation physical id: 101 bus info: pci@0000:ff:00.0 version: 04 width: 32 bits clock: 33MHz *-pci:2 description: Host bridge product: Core Processor QuickPath Architecture System Address Decoder vendor: Intel Corporation physical id: 102 bus info: pci@0000:ff:00.1 version: 04 width: 32 bits clock: 33MHz *-pci:3 description: Host bridge product: Core Processor QPI Link 0 vendor: Intel Corporation physical id: 103 bus info: pci@0000:ff:02.0 version: 04 width: 32 bits clock: 33MHz *-pci:4 description: Host bridge product: Core Processor QPI Physical 0 vendor: Intel Corporation physical id: 104 bus info: pci@0000:ff:02.1 version: 04 width: 32 bits clock: 33MHz *-pci:5 description: Host bridge product: Core Processor Integrated Memory Controller vendor: Intel Corporation physical id: 105 bus info: pci@0000:ff:03.0 version: 04 width: 32 bits clock: 33MHz *-pci:6 description: Host bridge product: Core Processor Integrated Memory Controller Target Address Decoder vendor: Intel Corporation physical id: 106 bus info: pci@0000:ff:03.1 version: 04 width: 32 bits clock: 33MHz *-pci:7 description: Host bridge product: Core Processor Integrated Memory Controller Test Registers vendor: Intel Corporation physical id: 107 bus info: pci@0000:ff:03.4 version: 04 width: 32 bits clock: 33MHz *-pci:8 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Control Registers vendor: Intel Corporation physical id: 108 bus info: pci@0000:ff:04.0 version: 04 width: 32 bits clock: 33MHz *-pci:9 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Address Registers vendor: Intel Corporation physical id: 109 bus info: pci@0000:ff:04.1 version: 04 width: 32 bits clock: 33MHz *-pci:10 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Rank Registers vendor: Intel Corporation physical id: 10a bus info: pci@0000:ff:04.2 version: 04 width: 32 bits clock: 33MHz *-pci:11 description: Host bridge product: Core Processor Integrated Memory Controller Channel 0 Thermal Control Registers vendor: Intel Corporation physical id: 10b bus info: pci@0000:ff:04.3 version: 04 width: 32 bits clock: 33MHz *-pci:12 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Control Registers vendor: Intel Corporation physical id: 10c bus info: pci@0000:ff:05.0 version: 04 width: 32 bits clock: 33MHz *-pci:13 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Address Registers vendor: Intel Corporation physical id: 10d bus info: pci@0000:ff:05.1 version: 04 width: 32 bits clock: 33MHz *-pci:14 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Rank Registers vendor: Intel Corporation physical id: 10e bus info: pci@0000:ff:05.2 version: 04 width: 32 bits clock: 33MHz *-pci:15 description: Host bridge product: Core Processor Integrated Memory Controller Channel 1 Thermal Control Registers vendor: Intel Corporation physical id: 10f bus info: pci@0000:ff:05.3 version: 04 width: 32 bits clock: 33MHz *-battery description: Lithium Ion Battery product: NK06053 vendor: SMP-ATL24 physical id: 1 slot: Primary capacity: 4800mWh configuration: voltage=11.1V lspci: 02:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 03) (prog-if 30 [XHCI]) Subsystem: Hewlett-Packard Company Device 1522 Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at d4000000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150] Latency Tolerance Reporting Kernel driver in use: xhci_hcd lsusb (with thumb drive plugged into USB3 port): Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 002 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub Bus 003 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 001 Device 002: ID 8087:0020 Intel Corp. Integrated Rate Matching Hub Bus 001 Device 003: ID 5986:01d0 Acer, Inc Bus 001 Device 004: ID 03f0:231d Hewlett-Packard

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  • Multi Pass Blend

    - by Kirk Patrick
    I am seeking the simplest working example of a two pass HLSL pixel shader. It can do anything really, but the main idea is to perform "ping ponging" to take the output of the first pass and then send it for the second pass. In my example I want to draw to the R channel and then draw to the G channel and produce a simple Venn Diagram in the shader, but need to detect overlap. I can currently detect one or the other but not overlap. There are a red and green circle overlapping, and I want to put a dynamic texture map in the overlap region. I can currently put it in either or. Below is how it looks in the shader. -------------------------------- Texture2D shaderTexture; SamplerState SampleType; ////////////// // TYPEDEFS // ////////////// struct PixelInputType { float4 position : SV_POSITION; float2 tex0 : TEXCOORD0; float2 tex1 : TEXCOORD1; float4 color : COLOR; }; //////////////////////////////////////////////////////////////////////////////// // Pixel Shader //////////////////////////////////////////////////////////////////////////////// float4 main(PixelInputType input) : SV_TARGET { float4 textureColor0; float4 textureColor1; // Sample the pixel color from the texture using the sampler at this texture coordinate location. textureColor0 = shaderTexture.Sample(SampleType, input.tex0); textureColor1 = shaderTexture.Sample(SampleType, input.tex1); if (input.color[0]==1.0f && input.color[1]==1.0f) // Requires multi-pass textureColor0 = textureColor1; return textureColor0; } Here is the calling code (that needs to be modified) m_d3dContext->IASetVertexBuffers(0, 2, vbs, strides, offsets); m_d3dContext->IASetIndexBuffer(m_indexBuffer.Get(), DXGI_FORMAT_R32_UINT,0); m_d3dContext->IASetPrimitiveTopology(D3D11_PRIMITIVE_TOPOLOGY_TRIANGLELIST); m_d3dContext->IASetInputLayout(m_inputLayout.Get()); m_d3dContext->VSSetShader(m_vertexShader.Get(), nullptr, 0); m_d3dContext->VSSetConstantBuffers(0, 1, m_constantBuffer.GetAddressOf()); m_d3dContext->PSSetShader(m_pixelShader.Get(), nullptr, 0); m_d3dContext->PSSetShaderResources(0, 1, m_SRV.GetAddressOf()); m_d3dContext->PSSetSamplers(0, 1, m_QuadsTexSamplerState.GetAddressOf());

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  • Class instance clustering in object reference graph for multi-entries serialization

    - by Juh_
    My question is on the best way to cluster a graph of class instances (i.e. objects, the graph nodes) linked by object references (the -directed- edges of the graph) around specifically marked objects. To explain better my question, let me explain my motivation: I currently use a moderately complex system to serialize the data used in my projects: "marked" objects have a specific attributes which stores a "saving entry": the path to an associated file on disc (but it could be done for any storage type providing the suitable interface) Those object can then be serialized automatically (eg: obj.save()) The serialization of a marked object 'a' contains implicitly all objects 'b' for which 'a' has a reference to, directly s.t: a.b = b, or indirectly s.t.: a.c.b = b for some object 'c' This is very simple and basically define specific storage entries to specific objects. I have then "container" type objects that: can be serialized similarly (in fact their are or can-be "marked") they don't serialize in their storage entries the "marked" objects (with direct reference): if a and a.b are both marked, a.save() calls b.save() and stores a.b = storage_entry(b) So, if I serialize 'a', it will serialize automatically all objects that can be reached from 'a' through the object reference graph, possibly in multiples entries. That is what I want, and is usually provides the functionalities I need. However, it is very ad-hoc and there are some structural limitations to this approach: the multi-entry saving can only works through direct connections in "container" objects, and there are situations with undefined behavior such as if two "marked" objects 'a'and 'b' both have a reference to an unmarked object 'c'. In this case my system will stores 'c' in both 'a' and 'b' making an implicit copy which not only double the storage size, but also change the object reference graph after re-loading. I am thinking of generalizing the process. Apart for the practical questions on implementation (I am coding in python, and use Pickle to serialize my objects), there is a general question on the way to attach (cluster) unmarked objects to marked ones. So, my questions are: What are the important issues that should be considered? Basically why not just use any graph parsing algorithm with the "attach to last marked node" behavior. Is there any work done on this problem, practical or theoretical, that I should be aware of? Note: I added the tag graph-database because I think the answer might come from that fields, even if the question is not.

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  • Real-Time Multi-User Gaming Platform

    - by Victor Engel
    I asked this question at Stack Overflow but was told it's more appropriate here, so I'm posting it again here. I'm considering developing a real-time multi-user game, and I want to gather some information about possibilities before I do some real development. I've thought about how best to ask the question, and for simplicity, the best way that occurred to me was to make an analogy to the field (or playground) game darebase. In the field game of darebase, there are two or more bases. To start, there is one team on each base. The game is a fancy game of tag. When two people meet out in the field, the person who left his base most recently timewise captures the other person. They then return to that person's base. Play continues until everyone is part of the same team. So, analogizing this to an online computer game, let's suppose there are an indefinite number of bases. When a person starts up the game, he has a team that is located at, for example, his current GPS coordinates. It could be a virtual world, but for sake of argument, let's suppose the virtual world corresponds to the player's actual GPS coordinates. The game software then consults the database to see where the closest other base is that is online, and the two teams play their game of virtual tag. Note that the user of the other base could have a different base than the one run by the current user as the closest base to him, in which case, he would be in two simultaneous battles, one with each base. When they go offline, the state of their players is saved on a server somewhere. Game logic calls for the players to have some automaton-logic of some sort, so they can fend for themselves in a limited way using basic rules, until their user goes online again. The user doesn't control the players' movements directly, but issues general directives that influence the players' movement logic. I think this analogy is good enough to frame my question. What sort of platforms are available to develop this sort of game? I've been looking at smartfoxserver, but I'm not convinced yet that it is the best option or even that it will work at all. One possibility, of course, would be to roll out my own web server, but I'd rather not do that if there is an existing service out there already that I could tap into. I will be developing for iOS devices at first. So any suggestions would be greatly appreciated. I think I need to establish the architecture first before proceeding with this project. Note that darbase is not the game I intend to implement, but, upon reflection, that might not be a bad idea either.

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  • Data structures for a 2D multi-layered and multi-region map?

    - by DevilWithin
    I am working on a 2D world editor and a world format subsequently. If I were to handle the game "world" being created just as a layered set of structures, either in top or side views, it would be considerably simple to do most things. But, since this editor is meant for 3rd parties, I have no clue how big worlds one will want to make and I need to keep in mind that eventually it will become simply too much to check, handling and comparing stuff that are happening completely away from the player position. I know the solution for this is to subdivide my world into sub regions and stream them on the fly, loading and unloading resources and other data. This way I know a virtually infinite game area is achievable. But, while I know theoretically what to do, I really have a few questions I'd hoped to get answered for some hints about the topic. The logic way to handle the regions is some kind of grid, would you pick evenly distributed blocks with equal sizes or would you let the user subdivide areas by taste with irregular sized rectangles? In case of even grids, would you use some kind of block/chunk neighbouring system to check when the player transposes the limit or just put all those in a simple array? Being a region a different data structure than its owner "game world", when streaming a region, would you deliver the objects to the parent structures and track them for unloading later, or retain the objects in each region for a more "hard-limit" approach? Introducing the subdivision approach to the project, and already having a multi layered scene graph structure on place, how would i make it support the new concept? Would you have the parent node have the layers as children, and replicate in each layer node, a node per region? Or the opposite, parent node owns all the regions possible, and each region has multiple layers as children? Or would you just put the region logic outside the graph completely(compatible with the first suggestion in Q.3) When I say virtually infinite worlds, I mean it of course under the contraints of the variable sizes and so on. Using float positions, a HUGE world can already be made. Do you think its sane to think beyond that? Because I think its ok to stick to this limit since it will never be reached so easily.. As for when to stream a region, I'm implementing it as a collection of watcher cameras, which the streaming system works with to know what to load/unload. The problem here is, i will be needing some kind of warps/teleports built in for my game, and there is a chance i will be teleporting a player to a unloaded region far away. How would you approach something like this? Is it sane to load any region to memory which can be teleported to by a warp within a radius from the player? Sorry for the huge question, any answers are helpful!

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  • Multi-threaded JOGL Problem

    - by moeabdol
    I'm writing a simple OpenGL application in Java that implements the Monte Carlo method for estimating the value of PI. The method is pretty easy. Simply, you draw a circle inside a unit square and then plot random points over the scene. Now, for each point that is inside the circle you increment the counter for in points. After determining for all the random points wither they are inside the circle or not you divide the number of in points over the total number of points you have plotted all multiplied by 4 to get an estimation of PI. It goes something like this PI = (inPoints / totalPoints) * 4. This is because mathematically the ratio of a circle's area to a square's area is PI/4, so when we multiply it by 4 we get PI. My problem doesn't lie in the algorithm itself; however, I'm having problems trying to plot the points as they are being generated instead of just plotting everything at once when the program finishes executing. I want to give the application a sense of real-time display where the user would see the points as they are being plotted. I'm a beginner at OpenGL and I'm pretty sure there is a multi-threading feature built into it. Non the less, I tried to manually create my own thread. Each worker thread plots one point at a time. Following is the psudo-code: /* this part of the code exists in display() method in MyCanvas.java which extends GLCanvas and implements GLEventListener */ // main loop for(int i = 0; i < number_of_points; i++){ RandomGenerator random = new RandomGenerator(); float x = random.nextFloat(); float y = random.nextFloat(); Thread pointThread = new Thread(new PointThread(x, y)); } gl.glFlush(); /* this part of the code exists in run() method in PointThread.java which implements Runnable */ void run(){ try{ gl.glPushMatrix(); gl.glBegin(GL2.GL_POINTS); if(pointIsIn) gl.glColor3f(1.0f, 0.0f, 0.0f); // red point else gl.glColor3f(0.0f, 0.0f, 1.0f); // blue point gl.glVertex3f(x, y, 0.0f); // coordinates gl.glEnd(); gl.glPopMatrix(); }catch(Exception e){ } } I'm not sure if my approach to solving this issue is correct. I hope you guys can help me out. Thanks.

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  • ARM processor for gigabit ethernet

    - by Surjya Narayana Padhi
    Hi Geeks, I am working on a project which is a handheld device to do some measurements on IP packets. So I need to process the packets by my processor. I am planning use ARM processor for this project. Can anybody suggest if ARM is the right choice for packet processing of Gigabit range?

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  • Missing processor/memory counters in the Windows XP Performance Monitor application (perfmon)

    - by Jader Dias
    Perfmon is a Windows utility that helps the developer to find bottlenecks in his applications, by measuring system counters. I was reading a perfmon tutorial and from this list of essential counters I have found the following ones on my machine: PhysicalDisk\Bytes/sec_Total Network Interface\Bytes Total/Sec\nic name But I haven't found the following counters nowhere: Processor\% Processor Time_Total Process\Working Set_Total Memory\Available MBytes Where do I find them? Note that my Windows is pt-BR (instead of en-US). Where do I find language specific documentation for windows tools like PerfMon?

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  • Could this code damage my processor??!!

    - by Osama Gamal
    A friend sent me that code and alleges that it could damage the processor. Is that true? void damage_processor() { while (true) { // Assembly code that sets the five control registers bits to ones which causes a bunch of exceptions in the system and then damages the processor Asm( "mov cr0, 0xffffffff \n\t" "mov cr1, 0xffffffff \n\t" "mov cr2, 0xffffffff \n\t" "mov cr3, 0xffffffff \n\t" "mov cr4, 0xffffffff \n\t" ) } } Is that true?

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  • Determining the load on a particular core in a multicore processor

    - by S.Man
    In a multicore processor, there are ways to tell the particular application to run in either single core or 2 cores or 3 cores. During such scenarios, how will a scheduler be able to determine the load(number of threads) on a particular core in a multicore processor and accordingly distribute(balance) the load(allocate threads) across the various cores ?

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  • How to implement multi-source XSLT mapping in 11g BPEL

    - by [email protected]
    In SOA 11g, you can create a XSLT mapper that uses multiple sources as the input. To implement a multi-source mapper, just follow the instructions below, Drag and drop a Transform Activity to a BPEL process Double-click on the Transform Activity, the Transform dialog window appears. Add source variables by clicking the Add icon and selecting the variable and part of the variable as needed. You can select multiple input variables. The first variable represents the main XML input to the XSL mapping, while additional variables that are added here are defined in the XSL mapping as input parameters. Select the target variable and its part if available. Specify the mapper file name, the default file name is xsl/Transformation_%SEQ%.xsl, where %SEQ% represents the sequence number of the mapper. Click OK, the xls file will be opened in the graphical mode. You can map the sources to the target as usual. Open the mapper source code, you will notice the variable representing the additional source payload, is defined as the input parameter in the map source spec and body<mapSources>    <source type="XSD">      <schema location="../xsd/po.xsd"/>      <rootElement name="PurchaseOrder" namespace="http://www.oracle.com/pcbpel/po"/>    </source>    <source type="XSD">      <schema location="../xsd/customer.xsd"/>      <rootElement name="Customer" namespace="http://www.oracle.com/pcbpel/Customer"/>      <param name="v_customer" />    </source>  </mapSources>...<xsl:param name="v_customer"/> Let's take a look at the BPEL source code used to execute xslt mapper. <assign name="Transform_1">            <bpelx:annotation>                <bpelx:pattern>transformation</bpelx:pattern>            </bpelx:annotation>            <copy>                <from expression="ora:doXSLTransformForDoc('xsl/Transformation_1.xsl',bpws:getVariableData('v_po'),'v_customer',bpws:getVariableData('v_customer'))"/>                <to variable="v_invoice"/>            </copy>        </assign> You will see BPEL uses ora:doXSLTransformForDoc XPath function to execute the XSLT mapper.This function returns the result of  XSLT transformation when the xslt template matching the document. The signature of this function is  ora:doXSLTransformForDoc(template,input, [paramQName, paramValue]*).Wheretemplate is the XSLT mapper nameinput is the string representation of xml input, paramQName is the parameter defined in the xslt mapper as the additional sourceparameterValue is the additional source payload. You can add more sources to the mapper at the later stage, but you have to modify the ora:doXSLTransformForDoc in the BPEL source code and make sure it passes correct parameter and its value pair that reflects the changes in the XSLT mapper.So the best practices are : create the variables before creating the mapping file, therefore you can add multiple sources when you define the transformation in the first place, which is more straightforward than adding them later on. Review ora:doXSLTransformForDoc code in the BPEL source and make sure it passes the correct parameters to the mapper.

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  • Enable Multi-Column Google Searches with a User Script

    - by Asian Angel
    Are you wanting to improve the search results view at Google and make better use of the webpage space? With a little user script magic you can make those search results look and fit better in your favorite browser. Note: This user script may conflict with the AutoPager extension if you have it installed in your favorite browser. Before Here is the standard single column view of search results at Google. Not too bad but the available space could certainly be better utilized. Note: For the purposes of our example we are using Google Chrome but this user script can be easily added to other browsers. After If you have never installed a user script in Chrome before it is just as simple as the regular extensions at the official Google website. Here you can see the details for the user script we are installing. Notice that you can view the source code if desired. To add the user script to Chrome click on “Install”. Once you start the install process you will see an intermediary message asking if you wish to continue in the lower left corner of your browser. Click “Continue” to move to the next step in the install process. From this point on the install process is practically identical to the official extensions. You can see the final confirmation window here…click “Install” to finish adding the user script to Chrome. As with regular extensions you will see a post-install message in the upper right corner. So, what does a user script look like in the “Extensions Page”? You can see the user script entry here…outside of an icon it looks rather identical to a normal extension. After refreshing the search page shown above we now have two columns of search results (default setting). This looks much much better than a single column view and there is little to no page scrolling required now. To switch to a three column view simply use the keyboard shortcut “Alt + 3”. To return to a single column view use “Alt + 1” and for the default two column view use “Alt + 2”. Three keyboard shortcuts for three different views…definitely a good thing. Note: On our test system we needed to use the number keys at the top of our keyboard to switch views…this is most likely the result of unique settings on our test system. Conclusion If you are wanting a better viewing experience when conducting searches at Google then this user script will make a very nice addition to your favorite browser. For those using Firefox you can add user scripts with the Greasemonkey & Stylish extensions. Using Opera Browser? See our how-to for adding user scripts to Opera here. Links Install the Multi-Column View of Google Search Results User Script Similar Articles Productive Geek Tips Hide Flash Animations in Google ChromeEnable Google Search From Shortcut Key in KDE on (k)UbuntuSet Gmail as Default Mail Client in UbuntuSet Up User Scripts in Opera BrowserHow To Enable Favicons for Google Reader Subscriptions TouchFreeze Alternative in AutoHotkey The Icy Undertow Desktop Windows Home Server – Backup to LAN The Clear & Clean Desktop Use This Bookmarklet to Easily Get Albums Use AutoHotkey to Assign a Hotkey to a Specific Window Latest Software Reviews Tinyhacker Random Tips DVDFab 6 Revo Uninstaller Pro Registry Mechanic 9 for Windows PC Tools Internet Security Suite 2010 Yes, it’s Patch Tuesday Generate Stunning Tag Clouds With Tagxedo Install, Remove and HIDE Fonts in Windows 7 Need Help with Your Home Network? Awesome Lyrics Finder for Winamp & Windows Media Player Download Videos from Hulu

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  • Just to not to be ignorant.

    - by atch
    Could anyone explain to me why is it that producers of processors claim that their processor can perform so many thousands (or millions) operations per second and yet typical program (Word, VS etc.) on my machine with 4GB, 3500hz starts with no less than 10 sec. Have to mention that I've just formatted disk and tick any necessary boxes to optimize my machine. So if for example outlook starts in 10 sec I wonder how many millions of operations have to be performed to run such program? Thanks

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  • Just to not to be ingnorant.

    - by atch
    Could anyone explain to me why is it that producers of processors claim that their processor can perform so many thousands (or millions) operations per second and yet typical program (Word, VS etc.) on my machine with 4GB, 3500hz starts with no less than 10sek. Have to mention that I've just formatted disk and tick any necessarry boxes to optimize my machine. So if for example outlook starts in 10 sek I wonder how many millions of operations have to be performed to run such program? Thanks

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  • Does Windows 7 Home Premium support Dual Core Processors?

    - by nicon
    I'm looking to buy a new laptop (the new studio 14 from Dell). The processor for this laptop is an Intel Core i5-520M. Think link http://reviews.cnet.com/8301-31012_7-10379487-10355804.html says that it supports only 1 CPU. Also Dell recommend the Professionnal version even tough Home Premium is the default choice. So I'm a little confuse as does Windows 7 Home Premium support Dual Core Processors ?

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