Flushing writes in buffer of Memory Controller to DDR device
- by Rohit
At some point in my code, I need to push the writes in my code all the way to the DIMM or DDR device. My requirement is to ensure the write reaches the row,ban,column of the DDR device on the DIMM. I need to read what I've written to the main memory. I do not want caching to get me the value. Instead after writing I want to fetch this value from main memory(DIMM's).
So far I've been using Intel's x86 instruction wbinvd(write back and invalidate cache). However this means the caches and TLB are flushed. Write-back requests go to the main memory.
However, there is a reasonable amount of time this data might reside in the write buffer of the Memory Controller( Intel calls it integrated memory controller or IMC). The Memory Controller
might take some more time depending on the algorithm that runs in the Memory Controller to handle writes.
Is there a way I force all existing or pending writes in the write buffer of the memory controller to the DRAM devices ??
What I am looking for is something more direct and more low-level than wbinvd. If you could point me to right documents or specs that describe this I would be grateful.
Generally, the IMC has a several registers which can be written or read from. From looking at the specs for that for the chipset I could not find anything useful.
Thanks for taking the time to read this.
