assign a value to reg in verilog
- by shen
for (j=0;j<k;j=j+1) begin:loop2
assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]};
end
row is a register,
it does not work as I am doing it. Can anyone please help me to fix it?
Thank you very much.
