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  • x86 Instruction Format: "ba 0e 00 00 00" ... "mov $0xe,%edx"

    - by Andrew Tomazos - Fathomling
    I'm getting the following line in the disassembly from objdump -d of an x86 linux program... 4000b0: ba 0e 00 00 00 mov $0xe,%edx I'm trying to understand how the machine code "ba 0e 00 00 00" maps to "mov $0xe,%edx" In the manual move immediate 32-bit is: B8 + rd ... MOV r32, imm32 ie "B8" not "BA" In fact none of the MOV opcodes are "BA". If someone could break down "ba 0e 00 00 00" and explain bit-wise how to get to "mov $0xe,%edx" it would be most helpful.

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  • What does the ".align" x86 Assembler directive do exactly? [migrated]

    - by Sinister Clock
    I will list exactly what I do not understand, and show you the parts I can not understand as well. First off, The .Align Directive .align integer, pad. The .align directive causes the next data generated to be aligned modulo integer bytes 1.~ ? : What is implied with "causes the next data generated to be aligned modulo integer bytes?" I can surmise that the next data generated is a memory-to-register transfer, no? Modulo would imply the remainder of a division. I do not understand "to be aligned modulo integer bytes"....... What would be a remainder of a simple data declaration, and how would the next data generated being aligned by a remainder be useful? If the next data is aligned modulo, that is saying the next generated data, whatever that means exactly, is the remainder of an integer? That makes absolutely no sense. What specifically would the .align, say, .align 8 directive issued in x86 for a data byte compiled from a C char, i.e., char CHARACTER = 0; be for? Or specifically coded directly with that directive, not preliminary Assembly code after compiling C? I have debugged in Assembly and noticed that any C/C++ data declarations, like chars, ints, floats, etc. will insert the directive .align 8 to each of them, and add other directives like .bss, .zero, .globl, .text, .Letext0, .Ltext0. What are all of these directives for, or at least my main asking? I have learned a lot of the main x86 Assembly instructions, but never was introduced or pointed at all of these strange directives. How do they affect the opcodes, and are all of them necessary?

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  • Why do VMs need to be "stack machines" or "register machines" etc.?

    - by Prog
    (This is an extremely newbie-ish question). I've been studying a little about Virtual Machines. Turns out a lot of them are designed very similarly to physical or theoretical computers. I read that the JVM for example, is a 'stack machine'. What that means (and correct me if I'm wrong) is that it stores all of it's 'temporary memory' on a stack, and makes operations on this stack for all of it's opcodes. For example, the source code 2 + 3 will be translated to bytecode similar to: push 2 push 3 add My question is this: JVMs are probably written using C/C++ and such. If so, why doesn't the JVM execute the following C code: 2 + 3..? I mean, why does it need a stack, or in other VMs 'registers' - like in a physical computer? The underlying physical CPU takes care of all of this. Why don't VM writers simply execute the interpreted bytecode with 'usual' instructions in the language the VM is programmed with? Why do VMs need to emulate hardware, when the actual hardware already does this for us? Again, very newbie-ish questions. Thanks for your help

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  • Quick, beginner MASM register question - DX:AX

    - by Francisco P.
    Hello, I am currently studying for an exam I'll have on x86 assembly. I didn't have much luck googling for ":", too common of a punctuation mark :/ IDIV - Signed Integer Division Usage: IDIV src Modifies flags: (AF,CF,OF,PF,SF,ZF undefined) Signed binary division of accumulator by source. If source is a byte value, AX is divided by "src" and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by "src", and the quotient is stored in AL and the remainder in DX. Taken from "Intel Opcodes and Mnemonics" What does DX:AX mean? Thanks a lot for your time :)

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  • Best resource for serious Commodore 64 programming.

    - by postfuturist
    What is the best resource for serious Commodore 64 programming? Assume that serious programming on the Commodore 64 is not done in BASIC V2 that ships with the Commodore 64. I feel like most of the knowledge is tied up in old books and not available on the internet. All that I have found online are either very beginner style introductions to Commodore 64 programming (Hello world), or arcane demo-coder hacks to take advantage of strange parts of the hardware. I haven't found a well-explained list of opcodes, memory locations for system calls, and general mid-level examples and tips. Main portals I have found: lemon64 C-64 Scene Database c64web Actually hosted on a Commodore 64! Tools I have found: cc65 A C compiler that can target Commodore 64.

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  • Why is the JVM stack-based and the DalvikVM register based?

    - by aioobe
    I'm curious, why did Sun decide to make the JVM stack-based and Google decide to make the DalvikVM register based? I suppose the JVM can't really assume that a certain number of registers are available on the target platform, since it is supposed to be platform independent. Therefor it just postpones the register-allocation etc, to the JIT compiler. (Correct me if I'm wrong.) So the Android guys thought, "hey, that's inefficient, let's go for a register based vm right away..."? But wait, there are multiple different android devices, what number of registers did the Dalvik target? Are the Dalvik opcodes hardcoded for a certain number of registers? Do all current Android devices on the market have about the same number of registers? Or, is there a register re-allocation performed during dex-loading? How does all this fit together?

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  • How does one use dynamic recompilation?

    - by acidzombie24
    It came to my attention some emulators and virtual machines use dynamic recompilation. How do they do that? In C i know how to call a function in ram using typecasting (although i never tried) but how does one read opcodes and generate code for it? Does the person need to have premade assembly chunks and copy/batch them together? is the assembly written in C? If so how do you find the length of the code? How do you account for system interrupts?

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  • Is any simple way to create method and set its body dynamically in C#?

    - by greatromul
    I hold body of method in string. I want to create method dynamically. But I don't know, how to set its body. I saw very tedious way using CodeDom. And I saw using Emit with OpCodes. Is any way to use ready code from string variable? string method_body = "return \"Hello, world!\";"; //there is method body DynamicMethod dm = new System.Reflection.Emit.DynamicMethod("My_method", typeof(string), new Type[] { }); //any way to create method dynamically //any way to set body string result = (string)dm.Invoke(...); //I need write result in variable

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  • Interpreters: How much simplification?

    - by Ray
    In my interpreter, code like the following x=(y+4)*z echo x parses and "optimizes" down to four single operations performed by the interpreter, pretty much assembly-like: add 4 to y multiply <last operation result> with z set x to <last operation result> echo x In modern interpreters (for example: CPython, Ruby, PHP), how simplified are the "opcodes" for which are in end-effect run by the interpreter? Could I achieve better performance when trying to keep the structures and commands for the interpreter more complex and high-level? That would be surely a lot harder, or?

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  • Untrusted GPGPU code (OpenCL etc) - is it safe? What risks?

    - by Grzegorz Wierzowiecki
    There are many approaches when it goes about running untrusted code on typical CPU : sandboxes, fake-roots, virtualization... What about untrusted code for GPGPU (OpenCL,cuda or already compiled one) ? Assuming that memory on graphics card is cleared before running such third-party untrusted code, are there any security risks? What kind of risks? Any way to prevent them ? (Possible sandboxing on gpgpu or other technique?) P.S. I am more interested in gpu binary code level security rather than hight-level gpgpu programming language security (But those solutions are welcome as well). What I mean is that references to gpu opcodes (a.k.a machine code) are welcome.

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  • Is it posibble to send websocket data over 126 chars?

    - by Udi Talias
    Its seems that everybody says that it is possible to send over 126 chars of data over websocket. I looked at many websocket server examples on the web and non of them can transfer over 126 chars from client to server and from server to client. I understand that it is something with dataframes and opcodes but i never figured it out. I'm using C#. Can somebody please put some light on this subject? any code example for receiving and sending data over 126 chars will be very very thankful

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  • How to find the jmp address during a x86 function call?

    - by Bruce
    Suppose we have a call foo statement. So when the assembler encounters a call statement it breaks it down into - push ip + 6 jmp <addr of foo> I have the return address in a register ebx. Now I want to find out the "addr of foo". How do I do it? I want to confirm that the push statement is present before the jmp. Will the memory map look something like this? ------- push (what will be the value stored in this byte?? opcode ??) ------- jmp (what will be the value stored in this byte?? opcode ??) ------- jmp byte 1 ------- jmp byte 2 ------- jmp byte 3 ------- jmp byte 4 ------- return address stored in ebx ------- What are the opcodes for push and jmp?

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  • Function calls in virtual machine killing performance

    - by GenTiradentes
    I wrote a virtual machine in C, which has a call table populated by pointers to functions that provide the functionality of the VM's opcodes. When the virtual machine is run, it first interprets a program, creating an array of indexes corresponding to the appropriate function in the call table for the opcode provided. It then loops through the array, calling each function until it reaches the end. Each instruction is extremely small, typically one line. Perfect for inlining. The problem is that the compiler doesn't know when any of the virtual machine's instructions are going to be called, as it's decided at runtime, so it can't inline them. The overhead of function calls and argument passing is killing the performance of my VM. Any ideas on how to get around this?

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  • Tracing all events in VB.NET

    - by MatsT
    I keep running into situations where I don't know what event I have to listen to in order to execute my code at the correct time. Is there any way to get a log of all events that is raised? Any way to filter that log based on what object raised the event? EDIT: Final solution: Private Sub WireAllEvents(ByVal obj As Object) Dim parameterTypes() As Type = {GetType(System.Object), GetType(System.EventArgs)} Dim Events = obj.GetType().GetEvents() For Each ev In Events Dim handler As New DynamicMethod("", Nothing, parameterTypes, GetType(main)) Dim ilgen As ILGenerator = handler.GetILGenerator() ilgen.EmitWriteLine("Event Name: " + ev.Name) ilgen.Emit(OpCodes.Ret) ev.AddEventHandler(obj, handler.CreateDelegate(ev.EventHandlerType)) Next End Sub And yes, I know this is not a good solution when you actually want to do real stuff that triggers off the events. There are good reasons for the 1 method - 1 event approach, but this is still useful when trying to figure out which of the methods you want to add your handlers to.

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  • C++ STL: Array vs Vector: Raw element accessing performance

    - by oh boy
    I'm building an interpreter and as I'm aiming for raw speed this time, every clock cycle matters for me in this (raw) case. Do you have any experience or information what of the both is faster: Vector or Array? All what matters is the speed I can access an element (opcode receiving), I don't care about inserting, allocation, sorting, etc. I'm going to lean myself out of the window now and say: Arrays are at least a bit faster than vectors in terms of accessing an element i. It seems really logical for me. With vectors you have all those security and controlling overhead which doesn't exist for arrays. (Why) Am I wrong? No, I can't ignore the performance difference - even if it is so small - I have already optimized and minimized every other part of the VM which executes the opcodes :)

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  • What's some simple F# code that generates the .tail IL instruction?

    - by kld2010
    I'd like to see the .tail IL instruction, but the simple recursive functions using tail calls that I've been writing are apparently optimized into loops. I'm actually guessing on this, as I'm not entirely sure what a loop looks like in Reflector. I definitely don't see any .tail opcodes though. I have "Generate tail calls" checked in my project's properties. I've also tried both Debug and Release builds in Reflector. The code I used is from Programming F# by Chris Smith, page 190: let factorial x = // Keep track of both x and an accumulator value (acc) let rec tailRecursiveFactorial x acc = if x <= 1 then acc else tailRecursiveFactorial (x - 1) (acc * x) tailRecursiveFactorial x 1 Can anyone suggest some simple F# code which will indeed generate .tail?

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  • A brief introduction to BRM and architecture

    - by Yani Miguel
    Oracle Communications Billing and Revenue Management (Oracle BRM) is the telcos industry´s leading solution intended for communications service providers. This post encourages to know BRM starting with the basics. History Portal was a billing and revenue managament solution to communications industry created by Portal Software. In 2006 Oracle acquired Portal Software and the solution was renamed BRM. Today Oracle BRM is the first end-to-end packaged enterprise software suite for the communications industry, however BRM is just one more product in the catalog of OSS solutions that Oracle offers. BRM can bill and manage all communications services including wireline, wireless, broadband, cable, voice over IP, IPTV, music, and video. BRM Architecture BRM´s architecture consists of 4 layers or tiers. Through these layers are the data, bussines logic and interfaces to connect graphical client tools.Application tier This layer provides GUI client tools enabling communication to other layers through open APIs. Some BRM client applications are: Customer Center Pricing Center Universal Event Loader Web Server BRM Billing Application Collections Center Permissioning Center Furthermore, this layer is where are provided real-time external events. Bussines Process Tier Although all layers are equally important, I think it deserves more atention because in this tier BRM functionality is implemented. All functions that give life to BRM are in this layer coded in C language called Opcodes (System Processes in the image). Any changes or additional functionality should be made here, so when we try to customize the product, we will most of the time programming in this layer (Business Policies in the image).Bussines Process Tier Features: Implements Portal system functionalityValidates data from the application tierModifies Portal behavior through business policies. Business policies can by customized.Triggers external systems using event notification. Object Tier This layer is responsible for transfer the BRM requests into database language and translate BRM requests into external system requests. Without it, the business logic (data from Bussines Process Tier) could not be understood by the relational database. Data tier Data tier is responsable for the storage of BRM database and other external systems databases. External systems include credit card, tax, and directory servers. Finally, It's important to note that BRM is designed to easily integrate with the following solutions:AIA 2.4 Siebel CRM E-Business Suite - G/L onlyCommunications Services Gatekeeper Oracle BI Publisher. Personally, I think that BRM could improve migrating client-server architecture to a fully web platform that works with Oracle Middleware like any product of the Fusion Middleware family. Hopefully there are already initiatives in this area.

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  • Fix ACPI DSDT of Amilo Pa 1538

    - by kayahr
    I have a Fujitsu-Siemens Amilo Pa 1538 laptops and installed Ubuntu 10.04 on it (Kernel 2.6.32). Main problem is that the fans of the notebook are always on even when the temperature is low. Another problem is that the display brightness can not be adjusted. Since some years I use Dell laptops and never experienced any ACPI problems so I thought that it is no longer needed to fix ACPI tables but now I have this crap of a laptop and I think I have to do it. Unfortunately I need some help repairing the DSDT. The dsdt.dat and dsdt.dsl of the laptop can be found here: http://www.ailis.de/~k/permdata/20100420/dsdt/ Compiling the DSDT gives the following output: # iasl -sa dsdt.dsl Intel ACPI Component Architecture ASL Optimizing Compiler version 20090521 [Jun 30 2009] Copyright (C) 2000 - 2009 Intel Corporation Supports ACPI Specification Revision 3.0a dsdt.dsl 81: Method (\_WAK, 1, NotSerialized) Warning 1080 - ^ Reserved method must return a value (_WAK) dsdt.dsl 207: Method (_L10, 0, NotSerialized) Warning 1087 - ^ Not all control paths return a value (_L10) dsdt.dsl 2861: Method (NVIF, 3, NotSerialized) Warning 1087 - ^ Not all control paths return a value (NVIF) dsdt.dsl 4551: Store (\_SB.PCI0.LPC0.PMRD (0xFA), Local0) Warning 1099 - Statement is unreachable ^ ASL Input: dsdt.dsl - 4962 lines, 162828 bytes, 2300 keywords AML Output: dsdt.aml - 17627 bytes, 591 named objects, 1709 executable opcodes Compilation complete. 0 Errors, 4 Warnings, 0 Remarks, 519 Optimizations Anyone here with DSDT experience who can help me fixing the DSDT?

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  • x86 opcode alignment references and guidelines

    - by mrjoltcola
    I'm generating some opcodes dynamically in a JIT compiler and I'm looking for guidelines for opcode alignment. 1) I've read comments that briefly "recommend" alignment by adding nops after calls 2) I've also read about using nop for optimizing sequences for parallelism. 3) I've read that alignment of ops is good for "cache" performance Usually these comments don't give any supporting references. Its one thing to read a blog or a comment that says, "its a good idea to do such and such", but its another to actually write a compiler that implements specific op sequences and realize most material online, especially blogs, are not useful for practical application. So I'm a believer in finding things out myself (disassembly, etc. to see what real world apps do). This is one case where I need some outside info. I notice compilers will usually start an odd byte instruction immediately after whatever previous instruction sequence there was. So the compiler is not taking any special care in most cases. I see "nop" here or there, but usually it seems nop is used sparingly, if at all. How critical is opcode alignment? Can you provide references for cases that I can actually use for implementation? Thanks.

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  • P6 Architecture - Register renaming aside, does the limited user registers result in more ops spent

    - by mrjoltcola
    I'm studying JIT design with regard to dynamic languages VM implementation. I haven't done much Assembly since the 8086/8088 days, just a little here or there, so be nice if I'm out of sorts. As I understand it, the x86 (IA-32) architecture still has the same basic limited register set today that it always did, but the internal register count has grown tremendously, but these internal registers are not generally available and are used with register renaming to achieve parallel pipelining of code that otherwise could not be parallelizable. I understand this optimization pretty well, but my feeling is, while these optimizations help in overall throughput and for parallel algorithms, the limited register set we are still stuck with results in more register spilling overhead such that if x86 had double, or quadruple the registers available to us, there may be significantly less push/pop opcodes in a typical instruction stream? Or are there other processor optmizations that also optimize this away that I am unaware of? Basically if I've a unit of code that has 4 registers to work with for integer work, but my unit has a dozen variables, I've got potentially a push/pop for every 2 or so instructions. Any references to studies, or better yet, personal experiences?

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  • How is a relative JMP (x86) implemented in an Assembler?

    - by Pindatjuh
    While building my assembler for the x86 platform I encountered some problems with encoding the JMP instruction: enc inst size in bytes EB cb JMP rel8 2 E9 cw JMP rel16 4 (because of 0x66 16-bit prefix) E9 cd JMP rel32 5 ... (from my favourite x86 instruction website, http://siyobik.info/index.php?module=x86&id=147) All are relative jumps, where the size of each encoding (operation + operand) is in the third column. Now my original (and thus fault because of this) design reserved the maximum (5 bytes) space for each instruction. The operand is not yet known, because it's a jump to a yet unknown location. So I've implemented a "rewrite" mechanism, that rewrites the operands in the correct location in memory, if the location of the jump is known, and fills the rest with NOPs. This is a somewhat serious concern in tight-loops. Now my problem is with the following situation: b: XXX c: JMP a e: XXX ... XXX d: JMP b a: XXX (where XXX is any instruction, depending on the to-be assembled program) The problem is that I want the smallest possible encoding for a JMP instruction (and no NOP filling). I have to know the size of the instruction at c before I can calculate the relative distance between a and b for the operand at d. The same applies for the JMP at c: it needs to know the size of d before it can calculate the relative distance between e and a. How do existing assemblers implement this, or how would you implement this? This is what I am thinking which solves the problem: First encode all the instructions to opcodes between the JMP and it's target, and if this region contains a variable-sized opcode, use the maximum size, i.e. 5 for JMP. Then in some conditions, the JMP is oversized (because it may fit in a smaller encoding): so another pass will search for oversized JMPs, shrink them, and move all instructions ahead), and set absolute branching instructions (i.e. external CALLs) after this pass is completed. I wonder, perhaps this is an over-engineered solution, that's why I ask this question.

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  • (x86) Assembler Optimization

    - by Pindatjuh
    I'm building a compiler/assembler/linker in Java for the x86-32 (IA32) processor targeting Windows. High-level concepts of a "language" (in essential a Java API for creating executables) are translated into opcodes, which then are wrapped and outputted to a file. The translation process has several phases, one is the translation between languages: the highest-level code is translated into the medium-level code which is then translated into the lowest-level code (probably more than 3 levels). My problem is the following; if I have higher-level code (X and Y) translated to lower-level code (x, y, U and V), then an example of such a translation is, in pseudo-code: x + U(f) // generated by X + V(f) + y // generated by Y (An easy example) where V is the opposite of U (compare with a stack push as U and a pop as V). This needs to be 'optimized' into: x + y (essentially removing the "useless" code) My idea was to use regular expressions. For the above case, it'll be a regular expression looking like this: x:(U(x)+V(x)):null, meaning for all x find U(x) followed by V(x) and replace by null. Imagine more complex regular expressions, for more complex optimizations. This should work on all levels. What do you suggest? What would be a good approach to optimize in these situations?

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  • Dynamically overriding an abstract method in c#

    - by ng
    I have the following abstract class public abstract class AbstractThing { public String GetDescription() { return "This is " + GetName(); } public abstract String GetName(); } Now I would like to implement some new dynamic types from this like so. AssemblyName assemblyName = new AssemblyName(); assemblyName.Name = "My.TempAssembly"; AssemblyBuilder assemblyBuilder = Thread.GetDomain().DefineDynamicAssembly(assemblyName, AssemblyBuilderAccess.Run); ModuleBuilder moduleBuilder = assemblyBuilder.DefineDynamicModule("DynamicThings"); TypeBuilder typeBuilder = moduleBuilder.DefineType(someName + "_Thing", TypeAttributes.Public | TypeAttributes.Class, typeof(AbstractThing)); MethodBuilder methodBuilder = typeBuilder.DefineMethod("GetName", MethodAttributes.Public | MethodAttributes.ReuseSlot | MethodAttributes.Virtual | MethodAttributes.HideBySig, null, Type.EmptyTypes); ILGenerator msil = methodBuilder.GetILGenerator(); msil.EmitWriteLine(selectionList); msil.Emit(OpCodes.Ret); However when I try to instantiate via typeBuilder.CreateType(); I get an exception saying that there is no implementation for GetName. Is there something I am doing wrong here. I can not see the problem. Also, what would be the restrictions on instantiating such a class by name? For instance if I tried to instantiate via "My.TempAssembly.x_Thing" would it be availble for instantiation without the Type generated?

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