How to generate makefile targets from variables?
- by Ketil
I currently have a makefile to process some data. The makefile gets the inputs to the data processing by sourcing a CONFIG file, which defines the input data in a variable. Currently, I symlink the input files to a local directory, i.e. the makefile contains:
tmp/%.txt: tmp
ln -fs $(shell echo $(INPUTS) | tr ' ' '\n' | grep $(patsubst tmp/%,%,$@)) $@
This is not terribly elegant, but appears to work. Is there a better way? Basically, given
INPUTS = /foo/bar.txt /zot/snarf.txt
I would like to be able to have e.g.
%.out: %.txt
some command
As well as targets to merge results depending on all $(INPUT) files.
Also, apart from the kludgosity, the makefile doesn't work correctly with -j, something that is crucial for the analysis to complete in reasonable time. I guess that's a bug in GNU make, but any hints welcome.