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  • GNU Makefile: multiple outputs from single rule + preventing intermediate files from being deleted

    - by makesaurus
    This is sort of a continuation of question from link text. The problem is that there is a rule generating multiple outputs from a single input, and the command is time-consuming so we would prefer to avoid recomputation. Now there is an additional twist, that we want to keep files from being deleted as intermediate files, and rules involve wildcards to allow for parameters. The solution suggested was that we set up the following rule: file-a.out: program file.in ./program file.in file-a.out file-b.out file-c.out file-b.out: file-a.out @ file-c.out: file-b.out @ Then, calling make file-c.out creates both and we avoid issues with running make in parallel with -j switch. All fine so far. The problem is the following. Because the above solution sets up a chain in the DAG, make considers it differently; the files file-a.out and file-b.out are treated as intermediate files, and they by default get deleted as unnecessary as soon as file-c.out is ready. A way of avoiding that was mentioned somewhere here, and consists of adding file-a.out and file-b.out as dependencies of a target .SECONDARY, which keeps them from being deleted. Unfortunately, this does not solve my case because my rules use wildcard patters; specifically, my rules look more like this: file-a-%.out: program file.in ./program $* file.in file-a-$*.out file-b-$*.out file-c-$*.out file-b-%.out: file-a-%.out @ file-c-%.out: file-b-%.out @ so that one can pass a parameter that gets included in the file name, for example by running make file-c-12.out The solution that make documentation suggests is to add these as implicit rules to the list of dependencies of .PRECIOUS, thus keeping these files from being deleted. The solution with .PRECIOUS works, but it also prevents these files from being deleted when a rule fails and files are incomplete. Is there any other way to make this work?

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  • Makefile automatic link dependency ?

    - by Kuang Chen
    It's easy to let program figure out the dependency at compile time, (with gcc -MM). Nevertheless, link dependency (deciding which libraries should be linked to) seems to be difficult to figure out. This issue become emergent when multiple targets with individual libraries to link to are needed. For instance, three dynamic library targets t1.so, t2.so and t3.so needs to be built. t1.so needs math library (-lm), while t2 and t3 don't. It would be tedious to write separate rules. A single rule requiring the three targets linked with math library saves the trouble. However, it causes inflation of target size since math library is unused for t2.so and t3.so. Any ideas?

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  • What is wrong in this simple Makefile

    - by Walidix
    SRC_VAR = test string for variable manipulation. TEST1_VAR = $(subset for,foo,${SRC_VAR}) all: @echo original str: ${SRC_VAR} @echo substitution: ${TEST1_VAR} This is the output: original str: test string for variable manipulation. substitution: The output should be: original str: My test string for variable manipulation. substitution: My test string foo variable manipulation.

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  • using makefile targets to set build options

    - by leo grrr
    This is either trivial or runs counter to the philosophy of how make should be used, but I'd like to have a command line that reads as "make debug" rather than "make DEBUG=1". I tried creating a phony target called debug that did nothing except set the DEBUG variable, but then there was a difference between "make debug build" and "make build debug"--namely that in one case, the variable got set after the build happened. Is there a way to give certain targets precedence? Thanks for your help.

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  • Makefile: expand dependencies

    - by Danyel
    First off, the title is very generic because there are just tons of ways of how to possibly solve this. However, I'm looking for a clean and neat way. Situation: I have two equal object files foo.o and foo-pi.o, the latter of which is position-independent (compiled with -fPIC). Both depend on foo.h and bar.h. Problem: How do I, without code duplication, declare dependency of all foo*.o to bar.h? Solutions so far: $(shell bash -c 'echo -ne foo{-pi,}.o'}: bar.h $(addsuffix .o, $(addprefix fo, o-pi o)): bar.h The first solution is not portable on systems that don't support bash, the second is a dirty solution since I could not figure out how to use empty strings in addprefix.

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  • Makefile rule depending on change of number of files instead of change in content of files.

    - by goathens
    I'm using a makefile to automate some document generation. I have several documents in a directory, and one of my makefile rules will generate an index page of those files. The list of files itself is loaded on the fly using list := $(shell ls documents/*.txt) so I don't have to bother manually editing the makefile every time I add a document. Naturally, I want the index-generation rule to trigger when number/title of files in the documents directory changes, but I don't know how to set up the prerequisites to work in this way. I could use .PHONY or something similar to force the index-generation to run all the time, but I'd rather not waste the cycles. I tried piping ls to a file list.txt and using that as a prerequisite for my index-generation rule, but that would require either editing list.txt manually (trying to avoid it), or auto-generating it in the makefile (this changes the creation time, so I can't use list.txt in the prerequisite because it would trigger the rule every time).

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  • How can I have a Makefile automatically rebuild source files that include a modified header file? (I

    - by Nicholas Flynt
    I have the following makefile that I use to build a program (a kernel, actually) that I'm working on. Its from scratch and I'm learning about the process, so its not perfect, but I think its powerful enough at this point for my level of experience writing makefiles. AS = nasm CC = gcc LD = ld TARGET = core BUILD = build SOURCES = source INCLUDE = include ASM = assembly VPATH = $(SOURCES) CFLAGS = -Wall -O -fstrength-reduce -fomit-frame-pointer -finline-functions \ -nostdinc -fno-builtin -I $(INCLUDE) ASFLAGS = -f elf #CFILES = core.c consoleio.c system.c CFILES = $(foreach dir,$(SOURCES),$(notdir $(wildcard $(dir)/*.c))) SFILES = assembly/start.asm SOBJS = $(SFILES:.asm=.o) COBJS = $(CFILES:.c=.o) OBJS = $(SOBJS) $(COBJS) build : $(TARGET).img $(TARGET).img : $(TARGET).elf c:/python26/python.exe concat.py stage1 stage2 pad.bin core.elf floppy.img $(TARGET).elf : $(OBJS) $(LD) -T link.ld -o $@ $^ $(SOBJS) : $(SFILES) $(AS) $(ASFLAGS) $< -o $@ %.o: %.c @echo Compiling $<... $(CC) $(CFLAGS) -c -o $@ $< #Clean Script - Should clear out all .o files everywhere and all that. clean: -del *.img -del *.o -del assembly\*.o -del core.elf My main issue with this makefile is that when I modify a header file that one or more C files include, the C files aren't rebuilt. I can fix this quite easily by having all of my header files be dependencies for all of my C files, but that would effectively cause a complete rebuild of the project any time I changed/added a header file, which would not be very graceful. What I want is for only the C files that include the header file I change to be rebuilt, and for the entire project to be linked again. I can do the linking by causing all header files to be dependencies of the target, but I cannot figure out how to make the C files be invalidated when their included header files are newer. I've heard that GCC has some commands to make this possible (so the makefile can somehow figure out which files need to be rebuilt) but I can't for the life of me find an actual implementation example to look at. Can someone post a solution that will enable this behavior in a makefile? EDIT: I should clarify, I'm familiar with the concept of putting the individual targets in and having each target.o require the header files. That requires me to be editing the makefile every time I include a header file somewhere, which is a bit of a pain. I'm looking for a solution that can derive the header file dependencies on its own, which I'm fairly certain I've seen in other projects.

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  • Can I have one makefile to build a hierarchical project?

    - by saramah
    I have several hundred files in a non-flat directory structure. My Makefile lists each sourcefile, which, given the size of the project and the fact that there are multiple developers on the project, can create annoyances when we forget to put a new one in or take out the old ones. I'd like to generalize my Makefile so that make can simply build all .cpp and .h files without me having to specify all the filenames, given some generic rules for different types of files. My question: given a large number of files in a directory with lots of subfolders, how do I tell make to build them all without having to specify each and every subfolder as part of the path? And how do I make it so that I can do this with only one Makefile in the root directory?

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  • How do I create a makefile from a Visual Studio solution file?

    - by Alex319
    I have a Visual Studio project that uses a solution file to build it. I want to generate a makefile so that I can build it using the makefile instead of the solution file. (The reason I need to do this in case you are wondering is that I am incorporating my project into a larger software system that uses makefiles to build, and I want to be able to build the whole thing using the makefiles.) Is there a way to automatically get the information from the Visual Studio solution and convert it into a makefile format, or do I need to do that manually?

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  • Is it a header file or library? in a makefile

    - by gccinac
    I already know the differences between a header file and a library. However, when I'm writing my makefile, I have some difficulties on deciding if I should put something as a dependency of the file or just at the linking rule. For example: I have 2 simple files: main.c: #include <stdio.h> main(){ printf("this is the sine or 90"); sinus(90); } and func.c: #include <math.h> sinus(int num){ return sin(num); } and my makefile is: main: main.o func.o gcc main.o func.o -lm -o main func.o: func.c main.o: main.c Well, my question is why this makefile works and this one doesn't: main: main.o func.o gcc main.o func.o -lm -o main func.o: func.c math.h main.o: main.c

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  • Wordpress - related posts by custom taxonomy problem

    - by Nordin
    Hello, I'm trying to display related posts based on a custum taxonomy. I found a query at wordpress.org that kind of works. However the original post gets duplicated in the results multiple times. (words is the name of the custom taxonomy I use) What seems to happen is that the single post gets duplicated according to what amount showpost is set. Any idea's what could cause this? The code: <?php //for in the loop, display all "content", regardless of post_type, //that have the same custom taxonomy (e.g. words) terms as the current post $backup = $post; // backup the current object $found_none = '<h2>No related posts found!</h2>'; $taxonomy = 'words';// e.g. post_tag, category, custom taxonomy $param_type = 'words'; // e.g. tag__in, category__in, but genre__in will NOT work $post_types = get_post_types( array('public' => true), 'names' ); $tax_args=array('orderby' => 'none'); $tags = wp_get_post_terms( $post->ID , $taxonomy, $tax_args); if ($tags) { foreach ($tags as $tag) { $args=array( "$param_type" => $tag->slug, 'post__not_in' => array($post->ID), 'post_type' => $post_types, 'showposts'=>5, 'caller_get_posts'=>1 ); $my_query = null; $my_query = new WP_Query($args); if( $my_query->have_posts() ) { while ($my_query->have_posts()) : $my_query->the_post(); ?> <h3><a href="<?php the_permalink() ?>" rel="bookmark" title="<?php the_title(); ?>"><?php the_title(); ?></a></h3> <?php $found_none = ''; endwhile; } } } if ($found_none) { echo $found_none; } $post = $backup; // copy it back wp_reset_query(); // to use the original query again ?>

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  • How to override a related sets "add" method?

    - by MB_
    I am working on a django project and i want to send a signal when something get's added to some models related set, e.g. we have an owner wo has a set of collectables and each time the method owner.collectable_set.add(something) is getting called i want signal like "collectable_added" or something. signals are clear to me, but in which manager(?) the "add" method sits that i want to override is unclear to me.

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  • Writing a "Hello World" Device Driver for kernel 2.6 using Eclipse

    - by Isaac
    Goal I am trying to write a simple device driver on Ubuntu. I want to do this using Eclipse (or a better IDE that is suitable for driver programming). Here is the code: #include <linux/module.h> static int __init hello_world( void ) { printk( "hello world!\n" ); return 0; } static void __exit goodbye_world( void ) { printk( "goodbye world!\n" ); } module_init( hello_world ); module_exit( goodbye_world ); My effort After some research, I decided to use Eclipse CTD for developing the driver (while I am still not sure if it supports multi-threading debugging tools). So I: Installed Ubuntu 11.04 desktop x86 on a VMWare virtual machine, Installed eclipse-cdt and linux-headers-2.6.38-8 using Synaptic Package Manager, Created a C Project named TestDriver1 and copy-pasted above code to it, Changed the default build command, make, to the following customized build command: make -C /lib/modules/2.6.38-8-generic/build M=/home/isaac/workspace/TestDriver1 The problem I get an error when I try to build this project using eclipse. Here is the log for the build: **** Build of configuration Debug for project TestDriver1 **** make -C /lib/modules/2.6.38-8-generic/build M=/home/isaac/workspace/TestDriver1 all make: Entering directory '/usr/src/linux-headers-2.6.38-8-generic' make: *** No rule to make target vmlinux', needed byall'. Stop. make: Leaving directory '/usr/src/linux-headers-2.6.38-8-generic' Interestingly, I get no error when I use shell instead of eclipse to build this project. To use shell, I just create a Makefile containing obj-m += TestDriver1.o and use the above make command to build. So, something must be wrong with the eclipse Makefile. Maybe it is looking for the vmlinux architecture (?) or something while current architecture is x86. Maybe it's because of VMWare? As I understood, eclipse creates the makefiles automatically and modifying it manually would cause errors in the future OR make managing makefile difficult. So, how can I compile this project on eclipse?

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  • sort django queryset by latest instance of a subset of related model

    - by rsp
    I have an Order model and order_event model. Each order_event has a foreignkey to order. so from an order instance i can get: myorder.order_event_set. I want to get a list of all orders but i want them to be sorted by the date of the last event. A statement like this works to sort by the latest event date: queryset = Order.objects.all().annotate(latest_event_date=Max('order_event__event_datetime')).order_by('latest_event_date') However, what I really need is a list of all orders sorted by latest date of A SUBSET OF EVENTS. For example my events are categorized into "scheduling", "processing", etc. So I should be able to get a list of all orders sorted by the latest scheduling event. This django doc (https://docs.djangoproject.com/en/dev/topics/db/aggregation/#filter-and-exclude) shows how I can get the latest schedule event using a filter but this excludes orders without a scheduling event. I thought I could combine the filtered queryset with a queryset that includes back those orders that are missing a scheduling event...but I'm not quite sure how to do this. I saw answers related to using python list but it would be much more useful to have a proper django queryset (ie for a view with pagination, etc.)

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  • nHibernate query looking for the related object's related object

    - by code-zoop
    I have an nHibernate querie issue that looks quite straight forward, but I can't seem to get my head around it! I am creating some simple example classes to illustrate my problem: public class Car { public int Id { get; set; } public IList<Interior> InteriorParts { get; set; } } public class Interior { public int Id { get; set; } public InteriorProducer Producer { get; set; } } public class InteriorProducer { public int Id { get; set; } } Now to the query: I have the id of the InteriorProducer, but need to get a list of Cars where the interior have been produced by the interior producer. So in a simple, pseudo SQL, it looks something like this: select cars where car.InteriorParts.Producer.Id = Id I have a really hard time getting my head around this to create an nHibernate query. Any Ideas? Thanks

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  • How can I write a makefile to auto-detect and parallelize the build with GNU Make?

    - by xyld
    Not sure if this is possible in one Makefile alone, but I was hoping to write a Makefile in a way such that trying to build any target in the file auto-magically detects the number of processors on the current system and builds the target in parallel for the number of processors. Something like the below "pseudo-code" examples, but much cleaner? all: @make -j$(NUM_PROCESSORS) all Or: all: .inparallel ... build all here ... .inparallel: @make -j$(NUM_PROCESSORS) $(ORIGINAL_TARGET) In both cases, all you would have to type is: % make all Hopefully that makes sense.

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  • Is there a way to generate a gitignore from a makefile?

    - by Kinopiko
    I have a lot of files such as JavaScript, HTML, and even C and C header (.h) files which are automatically generated, so they appear in the makefile like myfile.js: myfile.js.tmpl etc. I want all of these target files to be ignored by the version control system. I am using git but this question is not git-specific. Is there a utility or a trick which exists to make the ignore file (like .gitignore) from a makefile? (If there isn't such a facility, I can make a script to create one, but before I do that I am just checking I haven't missed some obvious tool or method.)

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  • Is there a way to automatically make a makefile from a template toolkit template?

    - by Smack my batch up
    My static web pages are built from a huge bunch of templates which are inter-included using Template Toolkit's "import" and "include", so page.html looks like this: [% INCLUDE top %] [% IMPORT middle %] Then top might have even more files included. I have very many of these files, and they have to be run through to create the web pages in various languages (English, French, etc., not computer languages). This is a very complicated process and when one file is updated I would like to be able to automatically remake only the necessary files, using a makefile or something similar. Are there any tools which can parse template toolkit templates and create a dependency list for use in a makefile? Or are there better ways to automate this process?

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  • desing pattern for related inputs

    - by curiousMo
    My question is a design question : let's say i have a data entry web page with 4 drop down lists, each depending on the previous one, and a bunch of text boxes. country (ddl), state (ddl), city (ddl), boro (ddl), address (txtBox), zipcode(txtbox). and an object that represents a datarow with a value for each. naturally the country, state, city and boro values will be values of primary keys of some lookup tables. when the user chooses to edits that record, i would load it from database and load it into the page. the issue that I have is how to streamline loading the ddls. i have some code that would grab the object, look thru its values and move them to their corresponding input controls in one shot. but in this case i will have to load possible values of country, then assign values, then load values of state, then assign value ans so on. I guess i am looking for an elegant solution. i am using asp.net, but i think it is irrelevant to the question. i am looking more into a design pattern. thanks

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  • design pattern for related inputs

    - by curiousMo
    My question is a design question : let's say i have a data entry web page with 4 drop down lists, each depending on the previous one, and a bunch of text boxes. ddlCountry (DropDownList) ddlState (DropDownList) ddlCity (DropDownList) ddlBoro (DropDownList) txtAddress (TxtBox) txtZipcode(TxtBox) and an object that represents a datarow with a value for each: countrySeqid stateSeqid citySeqid boroSeqid address zipCode naturally the country, state, city and boro values will be values of primary keys of some lookup tables. when the user chooses to edits that record, i would load it from database and load it into the page. the issue that I have is how to streamline loading the DropDownLists. i have some code that would grab the object,look thru its values and move them to their corresponding input controls in one shot. but in this case i will have to load the ddlCountry with possible values, then assign values, then do the same thing for the rest of the ddls. I guess i am looking for an elegant solution. i am using asp.net, but i think it is irrelevant to the question. i am looking more into a design pattern.

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