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  • Could this code damage my processor??!!

    - by Osama Gamal
    A friend sent me that code and alleges that it could damage the processor. Is that true? void damage_processor() { while (true) { // Assembly code that sets the five control registers bits to ones which causes a bunch of exceptions in the system and then damages the processor Asm( "mov cr0, 0xffffffff \n\t" "mov cr1, 0xffffffff \n\t" "mov cr2, 0xffffffff \n\t" "mov cr3, 0xffffffff \n\t" "mov cr4, 0xffffffff \n\t" ) } } Is that true?

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  • how to optimize illustrator artwork in flash?

    - by sasi
    I'm working on a flash project that incorporates a lot of artwork done in Illustrator CS4. I've been copy-pasting directly from Illustrator into Flash, and I add some animations as well. Final file is going to be a one single swf file which will be a part of UI for an application and .net will be the core for this. But now flash becomes unusable slow to respond for actions. My machine is a fast i7 with 6gb of RAM, so I don't think that's the issue. We are going to use this file with dual core atom processors. Does anyone have ideas for alternative importing techniques, optimizations within illustrator, anything at all that will make this more manageable? Thanks

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  • Working with ieee format numbers in ARM

    - by Jake Sellers
    I'm trying to write an ARM program that will convert an ieee number to a TNS format number. TNS is a format used by some super computers, and is similar to ieee but different. I'm trying to use several masks to place the three different "part" of the ieee number in separate registers so I can move them around accordingly. Here is my unpack subroutine: UnpackIEEE LDR r1, SMASK ;load the sign bit mask into r1 LDR r2, EMASK ;load the exponent mask into r2 LDR r3, GMASK ;load the significand mask into r3 AND r4, r0, r1 ;apply sign mask to IEEE and save into r4 AND r5, r0, r2 ;apply exponent mask to IEEE and save into r5 AND r6, r0, r3 ;apply significand mask to IEEE and save into r6 MOV pc, r14 ;return And here are the masks and number declarations so you can understand: IEEE DCD 0x40300000 ;2.75 decimal or 01000000001100000000000000000000 binary SMASK DCD 0x80000000 ;Sign bit mask EMASK DCD 0x7F800000 ;Exponent mask GMASK DCD 0x007FFFFF ;Significand mask When I step through with the debugger, the results I get are not what I expect after working through it on paper. EDIT: What I mean, is that after the subroutine runs, registers 4, 5, and 6 all remain 0. I can't figure out why the masks are not working. I think I do not fully understand how the number is being stored in the register or using the masks wrong. Any help appreciated. If you need more info just ask. EDIT: entry point: Very simple, just trying to get these subroutines working. ENTRY LDR r1, IEEE ;load IEEE num into r1 BL UnpackIEEE ;call unpack sub SWI SWI_Exit ;finish

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  • Unary NOT/Integersize of the architecture

    - by sid_com
    From "Mastering Perl/Chapter 16/Bit Operators/Unary NOT,~": The unary NOT operator (sometimes called the complement operator), ~, returns the bitwise negation, or 1's complement, of the value, based on integer size of the architecture Why does the following script output two different values? #!/usr/local/bin/perl use warnings; use 5.012; use Config; my $int_size = $Config{intsize} * 8; my $value = 0b1111_1111; my $complement = ~ $value; say length sprintf "%${int_size}b", $value; say length sprintf "%${int_size}b", $complement; Output: 32 64

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  • Why don't stacks grow upwards (for security)?

    - by AshleysBrain
    This is related to the question 'Why do stacks typically grow downwards?', but more from a security point of view. I'm generally referring to x86. It strikes me as odd that the stack would grow downwards, when buffers are usually written to upwards in memory. For example a typical C++ string has its end at a higher memory address than the beginning. This means that if there's a buffer overflow you're overwriting further up the call stack, which I understand is a security risk, since it opens the possibility of changing return addresses and local variable contents. If the stack grew upwards in memory, wouldn't buffer overflows simply run in to dead memory? Would this improve security? If so, why hasn't it been done? What about x64, do those stacks grow upwards and if not why not?

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  • Is there any .Net JIT Support from chip vendors?

    - by NoMoreZealots
    I know that ARM actually has some support for Java and SUN obviously, but I haven't really references seen any chip vendor supporting a .Net JIT compiler. I know IBM and Intel both support C compilers, as well as TI and many of the embedded chip vendors. When you think of it, all a JIT compiler is, is the last stages of compilation and optimization which you would think would be a good match for a chip vendor's expertize. Perhaps a standardized Plug In compilation engine for the VM would make sense. Microsoft is targeting .Net to embedded Windows platforms as well, so they are fair game. Pete

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  • two instances of tinymce with jquery ui causes chrome page to hang and be not responding

    - by Ahmed safan
    in the cpanel that i'm developing thre is a department for articles in arabic and english so i used two tinymce editors one for arabic and the other is for english it works as expected, but the problem is that when i'm using chrome browser the page suddenly become not responding and never come back and i need to restart it but in IE8 no problem at all. i've found in chrome task manager that the memory usage of the page is over 22 kilobyte. i'm also using jquery ui. i've tried the following 1- using jquery plugin the compressor tiny_mce_gzip.php 2- decreasing the plugins of tinymce [ispell,layers,..] what is the solution or what is the cause

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  • How is external memory, internal memory, and cache organized?

    - by goldenmean
    Consider a system as follows:= A hardware board having say ARM Cortex-A8 and Neon Vector coprocessor, and Embedded Linux OS running on Cortex-A8. On this environment, if there is some application - say, a video decoder is executing - then: How is it decided that which buffers would be in external memory, which ones would be allocated in internal SRAM, etc. When one says calloc/malloc on such system/code, the pointer returned is from which memory: internal or external? Can a user make buffers to be allocated to the memories of his choice (internal/external)? In ARM architectures, there is another memory called as Tightly coupled memory (TCM). What is that and how can user enable and use it? Can I declare buffers in this memory? Do I need to see the memory map (if any) of the hardware board to understand about all these different physical memories present in a typical hardware board? How much of a role does the OS play in distinguishing these different memories? Sorry for multiple questions, but i think they all are interlinked.

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  • Is recursion preferred compare to iteration in multicore era?

    - by prM
    Or say, do multicore CPUs process recursion faster than iteration? Or it simply depends on how one language runs on the machine? like c executes function calls with large cost, comparing to doing simple iterations. I had this question because one day I told one of my friend that recursion isn't any amazing magic that can speed up programs, and he told me that with multicore CPUs recursion can be faster than iteration. EDIT: If we consider the most recursion-loved situation (data structure, function call), is it even possible for recursion to be faster?

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  • Determine target architecture of binary file in Linux (library or executable)

    - by Fernando Miguélez
    We have an issue related to a Java application running under a (rather old) FC3 on a Advantech POS board with a Via C3 processor. The java application has several compiled shared libs that are accessed via JNI. Via C3 processor is suppossed to be i686 compatible. Some time ago after installing Ubuntu 6.10 on a MiniItx board with the same processor I found out that the previous statement is not 100% true. The Ubuntu kernel hanged on startup due to the lack of some specific and optional instructions of the i686 set in the C3 processor. These instructions missing in C3 implementation of i686 set are used by default by GCC compiler when using i686 optimizations. The solution in this case was to go with a i386 compiled version of Ubuntu distribution. The base problem with the Java application is that the FC3 distribution was installed on the HD by cloning from an image of the HD of another PC, this time an Intel P4. Afterwards the distribution needed some hacking to have it running such as replacing some packages (such as the kernel one) with the i383 compiled version. The problem is that after working for a while the system completely hangs without a trace. I am afraid that some i686 code is left somewhere in the system and could be executed randomly at any time (for example after recovering from suspend mode or something like that). My question is: Is there any tool or way to find out at what specific architecture is an binary file (executable or library) aimed provided that "file" does not give so much information?

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  • MySQL running on an EC2 m1.small instance has high load but low memory usage, possible resolutions?

    - by Tosh
    I have a MySQL server 5.0.75 Ubuntu, on an m1.small instance running on Amazon's EC2 as part of an application. During peak usage the server load will rise very high, while the memory usage stays low and the application server is no longer responsive since it's waiting for query results. The application server has only 5-8 apache processes running (mod_perl processes). The data directory uses only 140MB of data so the MyIsam tables aren't very big. The queries are pretty complicated with some big joins being performed, and the application makes a lot of queries. mysqltuner reports everything OK except "Maximum possible memory usage: 1.7G (99% of installed RAM)" but I'm nowhere close to using that. My question is, where should I be looking to fix this? Is this something that can be tuned away, or do I just need a larger instance/server? Googling indicates either or also upgrading MySQL server. Any pointers in the right direction would be greatly appreciated, thanks! EDIT: I just discovered this in my slow queries log: # Time: 101116 11:17:00 # User@Host: user[pass] @ [host] # Query_time: 4063 Lock_time: 1035 Rows_sent: 0 Rows_examined: 19960174 SELECT * FROM contacts WHERE contacts.contact_id IN (SELECT external_id FROM contact_relations WHERE external_table = 'contacts' AND contact_id IN (SELECT contact_id FROM contacts WHERE (company_name like '%%butan%%%' OR country like '%%butan%%%' OR city like '%%butan%%%' OR email1 like '%%butan%%%') AND (company_name is not null and company_name != ''))); Which actually brings up a different but related question: If I have a contact table containing: John Smith,The Fun Factory,555-1212,[email protected] What's the best way to search for that record using "factory" as a search key? Fulltext rarely seems to find items in the middle of a word, for example "actor" should bring up "Factory"

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  • How can I dual boot my iphone or ipad to run a very simple custom os?

    - by Jim98
    I am an experienced C/C++ programmer and have worked with assembly and many other programing language and I want to start a project as a learning process. I want to try and run a simple custom os on the iphone or ipad. What knowledge would I need to do this, and how does the iphone or ipad bootloader load the os and how could I modify it to load a custom os? Im not really sure what to ask here so I really just need to get as much information as possible so I could ask some more informed questions to get my project started Thanks

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  • Simple way to print value of a register in x86 assembly.

    - by Bob
    I need to write a program in 8086 Assembly that receives data from the user, does some mathematical calculations and prints the answer on the screen, I have written all parts of the program and all work fine but I don't know how to print the number to the screen. At the end of all my calculation the answer is AX and it is treated as an unsigned 16 bit integer. How do I print the decimal (unsigned) value of the AX register?

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  • What's the purpose of the rotate instructions (ROL, RCL on x86) ?

    - by lgratian
    I always wondered what's the purpose of the rotate instructions some CPUs have (ROL, RCL on x86, for example). What kind of software makes use of these instructions? I first thought they may be used for encryption/computing hash codes, but these libraries are written usually in C, which doesn't have operators that map to these instructions. Has anybody found an use for them? Why where they added to the instructions set?

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  • Porting 32 bit C++ code to 64 bit - is it worth it? Why?

    - by NTDLS
    I am aware of some the obvious gains of the x64 architecture (higher addressable RAM addresses, ect)... but: What if my program has no real need to run in native 64 bit mode. Should I port it anyway? Are there any foreseeable deadlines for ending 32 bit support? Would my application run faster / better / more secure as native x64 code?

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  • Grep without storing search to the "/ register in Vim

    - by Phro
    In my .vimrc I have a mapping that makes a line of text 'title capitalized': noremap <Leader>at :s/\v<(.)(\w{2,})/\u\1\L\2/g<CR> However, whenever I run this function, it highlights every word that is at least three characters long in my entire document. Of course I could get this behaviour to stop simply by appending :nohlsearch<CR> to the end of the mapping, but this is more of an awkward hack that still avoids a bigger problem: The last search has been replaced by \v<(.)(\w{2,}). Is there any way to use the search commands in Vim without storing the last search in the "/ register; a 'silent' search of sorts? That way, after running this title-making command, I can still use my previous search to navigate the document using n, N, etc. Edit Using @brettanomyces' answer, I found that simply setting the mapping: noremap <Leader>at :call setline(line('.'),substitute(getline('.'), '\v<(.)(\w{2,})', '\u\1\L\2', 'g'))<CR> will successfully perform the substitution without storing the searched text into the / register.

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  • How is the implicit segment register of a near pointer determined?

    - by Daniel Trebbien
    In section 4.3 of Intel 64® and IA-32 Architectures Software Developer's Manual. Volume 1: Basic Architecture, it says: A near pointer is a 32-bit offset ... within a segment. Near pointers are used for all memory references in a flat memory model or for references in a segmented model where the identity of the segment being accessed is implied. This leads me to wondering: how is the implied segment register determined? I know that (%eip) and displaced (%eip) (e.g. -4(%eip)) addresses use %cs by default, and that (%esp) and displaced (%esp) addresses use %ss, but what about (%eax), (%edx), (%edi), (%ebp) etc., and can the implicit segment register depend also on the instruction that the memory address operand appears in?

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  • Intel cpu hyperthreading on or off for ibm db2?

    - by rtorti19
    Has anyone ever done any database performance comparisons with hyper-threading enabled vs disabled? We are running ibm db2 and I'm curious if anyone has an recommendations for enabling hyper-threading or not. With hyper-threading enabled it makes it quite difficult to do capacity planning for cpu usage. For example. "With 8 physical cores represented as 16 "threads" on the OS and a cpu-bound workload, does that mean when your cpu usage hit's 50% you are actually running at 100%." What real benefits do I gain with leaving hyper-threading enabled on an intel server running DB2? Does hyper-threading help if you're workload is truly disk IO bound? If so, up to what percentage? These are the types of questions I'm trying to answer. Any thoughts?

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  • Z77 Motherboard with i7-2600K cpu, what will not work?

    - by Mxx
    I'm building a new system. So far I think I narrowed it down to Gigabyte GA-Z77X-UD5H (Z77 Ivy Bridge chipset) motherboard. I was planning to get i5-3570K(Ivy Bridge) cpu, but now I can get i7-2600K(Sandy Bridge) cpu for free. It is my understanding that Ivy Bridge platform brings support for PCIe3 and (additional?)USB3 ports. If I were to put SB cpu into IB motherboard, what is going to happen to PCIe3 slot? Will it not work at all or downgrade to PCIe2? Also, what is the situation with USB3 ports?

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