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• verilog or systemc for testbench

  - by Alphaneo

  I am assigned with the task of verifying some verilog based RTL code. Now, coding the RTL testbench using verilog seems to be very difficult (for me). So I would like to try one of the following. - Try providing a PLI interface to the RTL and thereby invoke 'C functions for testing - Using system 'C for interfacing the 'C functions PS: I already have a extensive 'C code that was used for testing the behavioral model. I am new to the world of hardware programming. Any pointers would be greatly appreciated.

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• VLC streaming testbench

  - by Vineet Menon

  Has anyone tried streaming media with VLC as server? I want to deploy VLC as streaming server, but my department didn't had a nice experience with VLC streaming. My question is has anyone tried VLC streaming over LAN with as many as 200 clients? What were the precautions to be taken before going for the actual showdown? What kind of transport stream is better for a smoother live streaming? Are any test bench I can use to convince my superiors?

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• Is Hyper-V server suitable as a desktop testbench?

  - by Thomas.Winsnes

  At the moment we are running a test bench with several desktop computers, that are reimaged every time we need to test on a different operation system. Also because different versions of our software is tested on each image, we have to install our software every time we want to test it. The problem we have had with going with a virtualization technology is that our software is depending on directx/opengl and 3D acceleration, and this has not been something that virtual machines have excelled at. With the release of SP1 for Windows 7 and Server 2008 R2 Hyper-V has gotten better 3D acceleration support, so we are looking into virtualizing our testbench using this. Our test scenario would most likely be something close to this: 1. Remote into the hyper-V server and load the test VM needed for the current tests 2. Remote into the VM and install the new version of the software 3. Run the tests It would be nice, but not essential, if our support team could remote into the VMs to match the users OS+software combination when doing support. Does anyone have any experience with this kind of settup with hyper-v?

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• issue with vhdl structural coding

  - by user3699982

  The code below is a simple vhdl structural architecture, however, the concurrent assignment to the signal, comb1, is upsetting the simulation with the outputs (tb_lfsr_out) and comb1 becoming undefined. Please, please help, thank you, Louise. library IEEE; use IEEE.STD_LOGIC_1164.all; entity testbench is end testbench; architecture behavioural of testbench is CONSTANT clock_frequency : REAL := 1.0e9; CONSTANT clock_period : REAL := (1.0/clock_frequency)/2.0; signal tb_master_clk, comb1: STD_LOGIC := '0'; signal tb_lfsr_out : std_logic_vector(2 DOWNTO 0) := "111"; component dff port ( q: out STD_LOGIC; d, clk: in STD_LOGIC ); end component; begin -- Clock/Start Conversion Generator tb_master_clk <= (NOT tb_master_clk) AFTER (1 SEC * clock_period); comb1 <= tb_lfsr_out(0) xor tb_lfsr_out(2); dff6: dff port map (tb_lfsr_out(2), tb_lfsr_out(1), tb_master_clk); dff7: dff port map (tb_lfsr_out(1), tb_lfsr_out(0), tb_master_clk); dff8: dff port map (tb_lfsr_out(0), comb1, tb_master_clk); end behavioural;

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