The code below is a simple vhdl structural architecture, however, the concurrent assignment to the signal, comb1, is upsetting the simulation with the outputs (tb_lfsr_out) and comb1 becoming undefined. Please, please help, thank you, Louise.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity testbench is
end testbench;

architecture behavioural of testbench is

CONSTANT clock_frequency : REAL := 1.0e9;
CONSTANT clock_period : REAL := (1.0/clock_frequency)/2.0;

signal tb_master_clk, comb1: STD_LOGIC := '0';

signal tb_lfsr_out : std_logic_vector(2 DOWNTO 0) := "111";

component dff
port
  (
    q: out STD_LOGIC;
    d, clk: in STD_LOGIC
  );
end component;

begin

-- Clock/Start Conversion Generator
tb_master_clk <= (NOT tb_master_clk) AFTER (1 SEC * clock_period);

comb1 <= tb_lfsr_out(0) xor tb_lfsr_out(2);

dff6: dff port map (tb_lfsr_out(2), tb_lfsr_out(1), tb_master_clk);
dff7: dff port map (tb_lfsr_out(1), tb_lfsr_out(0), tb_master_clk);
dff8: dff port map (tb_lfsr_out(0), comb1, tb_master_clk);

end behavioural;