JIT-ing on FPGAs ?

Posted by anon on Stack Overflow See other posts from Stack Overflow or by anon
Published on 2010-05-29T02:33:52Z Indexed on 2010/05/29 2:42 UTC
Read the original article Hit count: 391

Filed under:

jit

|

fpga

Many VMS, JVM/LLVM/... have JITs -- as the code is being interpreted, x86 instructions are created on the fly and executed.

If there something similar to this for FPGAS? Is there someway where as an FPGA is running, I reconfigure it? [If so, please provide project / paper links. If not, what is the technology bottleneck that prevents this from happening?]

Thanks!

© Stack Overflow or respective owner

Related posts about jit

.NET assembly cache / ngen / jit image warm-up and cool-down behavior

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi, I have an Input Method (IME) program built with C#.NET 2.0 DLL through C++/CLI. Since an IME is always attaching to another application, the C#.NET DLL seems not able to avoid image address rebasing. Although I have applied ngen to create a native image of that C#.NET 2.0 DLL and installed it… >>> More
What are the differences in JIT between Java and .Net

as seen on Stack Overflow - Search for 'Stack Overflow'
I know Microsoft .NET uses the NGEN utility to produce native machine code while Java has the Hotspot to do that. What Are the differences between those 2? >>> More
Building v8 without JIT

as seen on Stack Overflow - Search for 'Stack Overflow'
Hello, I would like to run some tests on v8 with and without JIT to compare performances. I know JIT will improve my average speed performance, but it would be nice for me to have some actual more detailed tests results as I want to work with mobile platforms. I haven't found how to enable or disable… >>> More
What does a JIT compiler do?

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi all, I was just watching the google IO videos and they talked about the JIT compiler they included in the android and showed a demo about performance improvements thanks to JIT compiler. I wondered what does exactly a JIT compiler do and wanted to hear from different people. So, What is the duty… >>> More
JIT compiler for C, C++, and the likes

as seen on Programmers - Search for 'Programmers'
Is there any just-in-time compiler out there for compiled languages, such as C and C++? (The first names that come to mind are Clang and LLVM! But I don't think they currently support it.) Explanation: I think the software could benefit from runtime profiling feedback and aggressively optimized… >>> More

Related posts about fpga

Java GUI amd FPGA

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi, I study on a robot simulator that written on Java environment.But sonar scan simulations and computational burden of some driven algorithms on robot drop my simulator's performance. So i have decided to use fpga module and put the computational burden on it.I have spartan 3a development kit… >>> More
Is FPGA course useful for a CS student?

as seen on Stack Overflow - Search for 'Stack Overflow'
I am a 3rd year computer science engineering student.Is it beneficial for me to go for FPGA course or seminar? >>> More
FPGA Filter Project

as seen on Stack Overflow - Search for 'Stack Overflow'
Do you guys have any good ideas on FPGA projects involving a filter? I want to do something interesting... not sure what. Thanks ahead of time. >>> More
Verilog code simulates but does not run as predicted on FPGA

as seen on Stack Overflow - Search for 'Stack Overflow'
I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin… >>> More
Looking for a micro programmable FPGA + machine

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi! I'm looking for a FPGA + machine. It should be entry level pricing (e.g no more than $200). EDIT: I want to make an ASM chart and program the FPGA to act like I specified in the chart >>> More