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Search found 35 results on 2 pages for 'fpga'.

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  • Java GUI amd FPGA

    - by murat
    Hi, I study on a robot simulator that written on Java environment.But sonar scan simulations and computational burden of some driven algorithms on robot drop my simulator's performance. So i have decided to use fpga module and put the computational burden on it.I have spartan 3a development kit for this implemenatation. Does anyone has any document or application sample that related with communication of java program on PC with fpga code. thanks.

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  • FPGA Place & Route

    - by anon
    For programming FPGAS, is it possible to write my own place & route routines? [The point is not that mine would be better; the point is whether I have the freedom to do so] -- or does the place & route stage output into undocumented bitfiles, essengially forcing me to use proprietary tools? Thanks!

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  • How difficult is it for an old-school programmer to pick up an FPGA kit and make something useful wi

    - by JUST MY correct OPINION
    I'm an old, old, old coder. (How old? I've used paper tape in anger.) I've programmed in a lot of languages and under a lot of paradigms (spaghetti, structured, object-oriented, functional and a smattering of logical). I'm getting bored. FPGAs look interesting to me. I have the crazy notion of resurrecting some of the ancient hardware I worked on in the days using FPGAs. I know this can be done because I've seen PDP-10 and PDP-11 implementations in FPGAs. I'd like to do the same for a few machines that are perhaps not as popular as those two, however. While I am an old, old coder, what I am not is an electronics or computer systems engineer. I'll be learning from scratch if I go down this path. My question, therefore, is two-fold: How difficult will it be for this old dinosaur to pick up and learn FPGAs to the point that interesting (not necessarily practical -- more from a hobbyist perspective) projects can be made? What should I start with learning-wise to go down this path? I know where to get FPGA kits, but I haven't found anything like "FPGAs for Complete Dinosaurs" yet anywhere out there.

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  • Best way to learn how to use FPGAs

    - by Myrrdyn
    In next weeks probably I will have some little FPGA to play with. I have a programmer background (C, C++, Java mostly) and some (very) limited experience in electronics. What are the best tools to know if you want to develop on FPGAs? What are the best languages to study? (what HW description languages?) Have you some examples of little "toy projects" that can be interesting, easy, and "eye-opener"? Thanks in advance. Edit: More details: if I understood correctly, the device I will be playing on will have an ARM core (no idea which one) and a 300k gates FPGA I'm looking specifically at some Linux free sw / open source tools...

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  • What FPGAs (Field-Programmable Gate Arrays) can one buy to experiment with at home?

    - by Joe Blow
    What the heck is an FPGA -- where can I buy one? What sort of system do you need to experiment with them? How to program them? Can you "load" if that's the right terms an FPGA using an ordinary mac or perhaps other *nix or windoze computer? Where can I buy some FPGAs today to experiment with ??! Are they expensive this only available to industry or can I buy one today? Does anyone know about this? Thanks! I have become interested in FPGAs after reading this question... Holistic Word Recognition algorithm in detail

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  • Development process for an embedded project with significant hardware changes

    - by pierr
    I have a good idea about Agile development process but it seems it does not fit well with a embedded project with significant hardware changes. I will describe below what we are currently doing (Ad-hoc way, no defined process yet). The changes are divided into three categories and different processes are used for each of them: complete hardware change example : use a different video codec IP a) Study the new IP b) RTL/FPGA simulation c) Implement the legacy interface - go to b) d) Wait until hardware (tape out) is ready f) Test on the real hardware hardware improvement example : enhance the image display quality by improving the underlying algorithm a) RTL/FPGA simulation b) Wait until hardware and test on the hardware Minor change example : only change hardware register mapping a) Wait until hardware and test on the hardware The worry is it seems we don't have too much control and confidence about software maturity for the hardware changes as the bring-up schedule is always very tight and the customer desired a seamless change when updating to a new version of hardware. How did you manage this kind of hardware change? Did you solve that by a Hardware Abstraction Layer (HAL)? Did you have a automatic test for the HAL layer? How did you test when the hardware platform is not even ready? Do you have well-documented processes for this kind of change?

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  • Developmnet process for an embedded project with significant Hardware change

    - by pierr
    Hi, I have a good idea about Agile development process but it seems it does not fit well with a embedded project with significant hardware change. I will describe below what we are currently doing (Ad-hoc way , no defined process yet). The change are divided to three categories and different process are used for them : complete hardware change example : use a different video codec IP a) Study the new IP b) RTL/FPGA simulation c) Implement the leagcy interface - go to b) d) Wait until hardware (tape out) is ready f) Test on the real Hardware hardware improvement example : enhance the image display quaulity by improving the underlie algorithm a)RTL/FPGA simulation b)Wait until hardware and test on the hardware Mino change exmaple : only change hardware register mapping a)Wait until hardware and test on the hardware The worry is it seems we don't have too much control and confidence about software maturity for the hardware change as the bring up schedule is always very tight and the customer desired a seemless change when updating to a new version hardware. How did you manage this kind of hardware hardware change? Did you solve that by a Hardware Abstraction Layer (HAL)? Did you have a automatical test for the HAL layer? How did you test when the hardware platform is not even ready? Do you have well documented process for this kind of change? Thanks for your insight.

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  • JIT-ing on FPGAs ?

    - by anon
    Many VMS, JVM/LLVM/... have JITs -- as the code is being interpreted, x86 instructions are created on the fly and executed. If there something similar to this for FPGAS? Is there someway where as an FPGA is running, I reconfigure it? [If so, please provide project / paper links. If not, what is the technology bottleneck that prevents this from happening?] Thanks!

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  • Should you remove all warnings in your Verilog or VHDL design? Wh or why not?

    - by Brian Carlton
    In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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  • Fast partial sorting algorithm

    - by trican
    I'm looking for a fast way to do a partial sort of 81 numbers - Ideally I'm looking to extract the lowest 16 values (its not necessary for the 16 to be in the absolutely correct order). The target for this is dedicated hardware in an FPGA - so this slightly complicated matters as I want the area of the resultant implementation as small as possible. I looked at and implemented the odd-even merge sort algorithm, but I'm ideally looking for anything that might be more efficient for my needs (trade algorithm implementation size for a partial sort giving lowest 16, not necessarily in order as opposed to a full sort) Any suggestions would be very welcome Many thanks

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  • Should you remove all warnings in your Verilog or VHDL design? Why or why not?

    - by Brian Carlton
    In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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  • Modelsim (XE III/Starter 6.4b) not allowing me to define a macro function

    - by montooner
    I'm working on a Xiling FPGA for a course project. Normally we use the lab computers, but I'm trying to install on my own computer. So, I'm trying to include a macro file using line: `include "Const.v" But the following macro function doesn't work. Any ideas why? `ifdef synthesis // if Synplify `define SYNPLIFY `define SYNTHESIS `define MACROSAFE `else // if not Synplify `ifdef MODELSIM `define SIMULATION `define MACROSAFE `else `define XST // synthesis translate_off // if XST then stop compiling `undef XST `define SIMULATION `define MODELSIM // synthesis translate_on // if XST then resume compiling `ifdef XST `define SYNTHESIS `define MACROSAFE `endif `endif `endif //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Section: Log2 Macro // Desc: A macro to take the log base 2 of any number. Useful for // calculating bitwidths. Warning, this actually calculates // log2(x-1), not log2(x). //------------------------------------------------------------------------------ `ifdef MACROSAFE `define log2(x) ((((x) > 1) ? 1 : 0) + \ (((x) > 2) ? 1 : 0) + \ (((x) > 4) ? 1 : 0) + \ (((x) > 8) ? 1 : 0) + \ (((x) > 16) ? 1 : 0) + \ (((x) > 32) ? 1 : 0) + \ (((x) > 64) ? 1 : 0) + \ (((x) > 128) ? 1 : 0) + \ (((x) > 256) ? 1 : 0) + \ (((x) > 512) ? 1 : 0) + \ (((x) > 1024) ? 1 : 0) + \ (((x) > 2048) ? 1 : 0) + \ (((x) > 4096) ? 1 : 0) + \ (((x) > 8192) ? 1 : 0) + \ (((x) > 16384) ? 1 : 0) + \ (((x) > 32768) ? 1 : 0) + \ (((x) > 65536) ? 1 : 0) + \ (((x) > 131072) ? 1 : 0) + \ (((x) > 262144) ? 1 : 0) + \ (((x) > 524288) ? 1 : 0) + \ (((x) > 1048576) ? 1 : 0) + \ (((x) > 2097152) ? 1 : 0) + \ (((x) > 4194304) ? 1 : 0) + \ (((x) > 8388608) ? 1 : 0) + \ (((x) > 16777216) ? 1 : 0) + \ (((x) > 33554432) ? 1 : 0) + \ (((x) > 67108864) ? 1 : 0) + \ (((x) > 134217728) ? 1 : 0) + \ (((x) > 268435456) ? 1 : 0) + \ (((x) > 536870912) ? 1 : 0) + \ (((x) > 1073741824) ? 1 : 0)) `endif

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  • Looking for library declaration of IP Module

    - by Martin
    Hi, I want to use the Xilinx hardware module of the ICAP controller in my own design. This module uses the following library: library hwicap_v5_00_a; use hwicap_v5_00_a.all; I was looking in the directories as well as subdirectories of Xilinx\12.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores but I could not find the package declaration of hwicap. Anyone an idea where Xilinx "hides" this information. Many thanks

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  • Signals and Variables in VHDL - Problem

    - by Morano88
    I have a signal and this signal is a bitvector. The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a signal after defining the variables ? It is ggiving me errors when I do that. It is working fine If I keep the signal before the variables .. but I don't want that .. the length of Z depends on the computations of the variables. What is the solution ? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BSD_Full_Comp is Generic (n:integer:=8); Port(X, Y : inout std_logic_vector(n-1 downto 0); FZ : out std_logic_vector(1 downto 0)); end BSD_Full_Comp; architecture struct of BSD_Full_Comp is Component BSD_BitComparator Port ( Ai_1 : inout STD_LOGIC; Ai_0 : inout STD_LOGIC; Bi_1 : inout STD_LOGIC; Bi_0 : inout STD_LOGIC; S1 : out STD_LOGIC; S0 : out STD_LOGIC ); END Component; Signal Z : std_logic_vector(2*n-3 downto 0); begin ass : process Variable length : integer := n; Variable pow : integer :=0 ; Variable ZS : integer :=0; begin while length /= 0 loop length := length/2; pow := pow+1; end loop; length := 2 ** pow; ZS := length - n; wait; end process; end struct;

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  • Signals and Variables in VHDL (order) - Problem

    - by Morano88
    I have a signal and this signal is a bitvector (Z). The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a signal after defining the variables ? It is giving me errors when I do that. It is working fine If I keep the signal before the variables (that what is showing below) .. but I don't want that .. the length of Z depends on the computations of the variables. What is the solution ? library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BSD_Full_Comp is Generic (n:integer:=8); Port(X, Y : inout std_logic_vector(n-1 downto 0); FZ : out std_logic_vector(1 downto 0)); end BSD_Full_Comp; architecture struct of BSD_Full_Comp is Component BSD_BitComparator Port ( Ai_1 : inout STD_LOGIC; Ai_0 : inout STD_LOGIC; Bi_1 : inout STD_LOGIC; Bi_0 : inout STD_LOGIC; S1 : out STD_LOGIC; S0 : out STD_LOGIC ); END Component; Signal Z : std_logic_vector(2*n-3 downto 0); begin ass : process Variable length : integer := n; Variable pow : integer :=0 ; Variable ZS : integer :=0; begin while length /= 0 loop length := length/2; pow := pow+1; end loop; length := 2 ** pow; ZS := length - n; wait; end process; end struct;

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  • What is the minimum delay between two consecutive RS232 frames?

    - by Lord Loh.
    I have been working on creating a UART on an FPGA. I can successfully transmit and receive single characters typed on PuTTY. However, when I set my FPGA to constantly write a large sequences of "A", sometimes I end up with a sequences of "@" or some other characters until I reset the FPGA a few times. I believe the UART on the computer looses track of the difference between the start bit and a zero. The delay between the two "A" is ~ 30us (measured with a logic analyzer) and the baud rate is 115200 8N1. Is there a minimum delay that must be maintained between two consecutive RS232 frames?

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  • Is an Ethernet point to point connection without a switch real time capable?

    - by funksoulbrother
    In automation and control, it is commonly stated that ethernet can't be used as a bus because it is not real time capable due to packet collisions. If important control packets collide, they often can't keep the hard real time conditions needed for control. But what if I have a single point to point connection with Ethernet, no switch in between? To be more precise, I have an FPGA board with a giga-Ethernet port that is connected directly to my control PC. I think the benefits of giga Ethernet over CAN or USB for a p2p connection are huge, especially for high sampling rates and lots of data generation on the FPGA board. Am I correct that with a point to point connection there can't be any packet collisions and therefore a real time environment is given even with ethernet? Thanks in advance! ~fsb

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  • Is an Ethernet point to point connection without a switch real time capable?

    - by funksoulbrother
    In automation and control, it is commonly stated that ethernet can't be used as a bus because it is not real time capable due to packet collisions. If important control packets collide, they often can't keep the hard real time conditions needed for control. But what if I have a single point to point connection with Ethernet, no switch in between? To be more precise, I have an FPGA board with a giga-Ethernet port that is connected directly to my control PC. I think the benefits of giga Ethernet over CAN or USB for a p2p connection are huge, especially for high sampling rates and lots of data generation on the FPGA board. Am I correct that with a point to point connection there can't be any packet collisions and therefore a real time environment is given even with ethernet? Thanks in advance! ~fsb

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  • Programmatic use of ARP

    - by sizzzzlerz
    I have a need for some C or C++ code, compilable under Linux, to be able to take a list of IP addresses of some arbitrary number of remote hosts machines and obtain a ethernet MAC address for each one. These host machines may be on the same subnet or they could be on a different subnet behind a router. Its OK if the MAC address of some or all of the remote hosts is the address of the interface on the router. Ultimately, I want to hand off the IP address and MAC address to an FPGA who will use these pieces of information to format and send UDP/IP packets over ethernet to the hosts. Obviously, the FPGA will also be given its own MAC address and IP address to fill in the source MAC and source IP addresses in the packets. Is there some code I can be pointed to that can create and broadcast ARP packets to these remote machines and receive back the ARP response packets such that the destination MAC addresses can be extracted?

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  • Python: Serial Transmission

    - by Silent Elektron
    I have an image stack of 500 images (jpeg) of 640x480. I intend to make 500 pixels (1st pixels of all images) as a list and then send that via COM1 to FPGA where I do my further processing. I have a couple of questions here: How do I import all the 500 images at a time into python and how do i store it? How do I send the 500 pixel list via COM1 to FPGA? I tried the following: Converted the jpeg image to intensity values (each pixel is denoted by a number between 0 and 255) in MATLAB, saved the intensity values in a text file, read that file using readlines(). But it became too cumbersome to make the intensity value files for all the 500 images! Used NumPy to put the read files in a matrix and then pick the first pixel of all images. But when I send it, its coming like: [56, 61, 78, ... ,71, 91]. Is there a way to eliminate the [ ] and , while sending the data serially? Thanks in Advance! :)

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  • HP Z400 workstation with RHEL5 LINUX OS; NO MORE REACHABLE, need to reboot

    - by alain
    The LiNUX RHEL5 Workstation Z400 stop answering to ping and it was no more possible to connect to it, even on the local console; The workstation was not reachable in anay way. The only method I found is to restart the station (switch off, switch on) and after that everything works fine Have somebody an idea on what can have happened I don't see explanation of this in the /var/log/messages Some more informations: Placement/routing of a FPGA was running

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