Verilog code simulates but does not run as predicted on FPGA

Posted by chester.boo on Stack Overflow See other posts from Stack Overflow or by chester.boo
Published on 2010-03-12T19:55:46Z Indexed on 2010/03/13 5:25 UTC
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verilog

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synthesis

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xilinx

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fpga

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hdl

I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin.com/XWMekL7r

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