Hi, i'm coding a 4-bit binary adder with accumulator:

library ieee;
use ieee.std_logic_1164.all;

entity binadder is
    port(n,clk,sh:in bit;
    	x,y:inout std_logic_vector(3 downto 0);
    	co:inout bit;
    	done:out bit);
end binadder;

architecture binadder of binadder is
    signal state: integer range 0 to 3;
    signal sum,cin:bit;
begin
    sum<= (x(0) xor y(0)) xor cin;
    co<= (x(0) and y(0)) or (y(0) and cin) or (x(0) and cin);

    process
    begin
    	wait until clk='0';
    	case state is
    		when 0=>
    			if(n='1') then
    				state<=1;
    			end if;
    		when 1|2|3=>
    			if(sh='1') then
    				x<= sum & x(3 downto 1);
    				y<= y(0) & y(3 downto 1);
    				cin<=co;
    			end if;
    			if(state=3) then
    				state<=0;
    			end if;
    	end case;
    end process;

    done<='1' when state=3 else '0';
end binadder;

The output :

-- Compiling architecture binadder of binadder

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):

No feasible entries for infix operator "xor".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(15):

Type error resolving infix expression "xor" as type std.standard.bit.

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

No feasible entries for infix operator "and".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Bad expression in right operand of infix expression "or".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

No feasible entries for infix operator "and".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Bad expression in left operand of infix expression "or".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Bad expression in right operand of infix expression "or".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(16):

Type error resolving infix expression "or" as type std.standard.bit.

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):

No feasible entries for infix operator "&".

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(28):

Type error resolving infix expression "&" as type ieee.std_logic_1164.std_logic_vector.

** Error: C:/Modeltech_pe_edu_6.5a/examples/binadder.vhdl(39):

VHDL Compiler exiting

I believe i'm not handling std_logic_vector's correctly. Please tell me how? :(