error when synthesizing VHDL code

Posted by EquinoX on Stack Overflow See other posts from Stack Overflow or by EquinoX
Published on 2010-04-21T23:14:08Z Indexed on 2010/04/22 0:13 UTC
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Filed under:

vhdl

|

verilog

|

synthesis

I am getting the warning that:

One or more signals are missing in the sensitivity list of always block.

  always@(Address)begin
        ReadData = instructMem[Address];
    end

How do I get rid of this warning?

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