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  • assign a value to reg in verilog

    - by shen
    for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register, it does not work as I am doing it. Can anyone please help me to fix it? Thank you very much.

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  • Verilog linting tools?

    - by mrflibble
    What are your favorite linting tools for verilog? I am currently looking for a good verilog linting tool. And preferably one that can be configured to either handle or ignore certain vendor specific primitives like LUT's, PLL's, etc. I recently tried verilator-3.810, but out of the box it needs a little help with the primitives. So what (linting) tools do you use to deal with the not-so-strict syntax of verilog?

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  • verilog / systemverilog -- What is the behavior of blocking statements across two always blocks?

    - by miles.sherman
    I am wondering about the behavior of the below code. There are two always blocks, one is combinational to calculate the next_state signal, the other is sequential which will perform some logic and determine whether or not to shutdown the system. It does this by setting the shutdown_now signal high and then calling state <= next_state. My question is if the conditions become true that the shutdown_now signal is set (during clock cycle n) in a blocking manner before the state <= next_state line, will the state during clock cycle n+1 be SHUTDOWN or RUNNING? In other words, does the shutdown_now = 1'b1 line block across both state machines since the state signal is dependent on it through the next_state determination? enum {IDLE, RUNNING, SHUTDOWN} state, next_state; logic shutdown_now; // State machine (combinational) always_comb begin case (state) IDLE: next_state <= RUNNING; RUNNING: next_state <= shutdown ? SHUTDOWN : RUNNING; SHUTDOWN: next_state <= SHUTDOWN; default: next_state <= SHUTDOWN; endcase end // Sequential Behavior always_ff @ (posedge clk) begin // Some code here if (/*some condition) begin shutdown_now = 1'b0; end else begin shutdown_now = 1'b1; end state <= next_state; end

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  • verilog or systemc for testbench

    - by Alphaneo
    I am assigned with the task of verifying some verilog based RTL code. Now, coding the RTL testbench using verilog seems to be very difficult (for me). So I would like to try one of the following. - Try providing a PLI interface to the RTL and thereby invoke 'C functions for testing - Using system 'C for interfacing the 'C functions PS: I already have a extensive 'C code that was used for testing the behavioral model. I am new to the world of hardware programming. Any pointers would be greatly appreciated.

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  • How to make multiple wires quickly in Verilog?

    - by user1334858
    I am trying to make 24 wires in total very quickly but I keep getting the error: Error (10170): Verilog HDL syntax error at your_ALU_mux.v(81) near text "="; expecting ".", or an identifier Here is my code: module your_ALU_mux(your_out, operandA, operandB, opcode, switches, address); input [7:0] operandA, operandB, address; input [3:0] opcode, switches; output [7:0] your_out; wire [0:7] Bnot, newb, newa; wire Cin, Cout; not (Bnot[0], operandB[0]), (Bnot[1], operandB[1]), (Bnot[2], operandB[2]), (Bnot[3], operandB[3]), (Bnot[4], operandB[4]), (Bnot[5], operandB[5]), (Bnot[6], operandB[6]), (Bnot[7], operandB[7]); // Getting A' and B' if (address == 16'h00 || address == 16'h01) // Add A + B if (address == 16'h00) // newa = A newa[0] = operandA[0]; newa[1] = operandA[1]; newa[2] = operandA[2]; newa[3] = operandA[3]; newa[4] = operandA[4]; newa[5] = operandA[5]; newa[6] = operandA[6]; newa[7] = operandA[7]; // newb = B' newb[0] = Bnot[0]; newb[1] = Bnot[1]; newb[2] = Bnot[2]; newb[3] = Bnot[3]; newb[4] = Bnot[4]; newb[5] = Bnot[5]; newb[6] = Bnot[6]; newb[7] = Bnot[7]; // Carry in = 1 Cin = 1; // A-B else if (address == 16'h01) // newb = B newb[0] = operandB[0]; newb[1] = operandB[1]; newb[2] = operandB[2]; newb[3] = operandB[3]; newb[4] = operandB[4]; newb[5] = operandB[5]; newb[6] = operandB[6]; newb[7] = operandB[7]; // newa = A newa[0] = operandA[0]; newa[1] = operandA[1]; newa[2] = operandA[2]; newa[3] = operandA[3]; newa[4] = operandA[4]; newa[5] = operandA[5]; newa[6] = operandA[6]; newa[7] = operandA[7]; // Carry in = 0 Cin = 0; end RippleCarryAdd A+B(.S0(your_out[0]), .S1(your_out[1],.S2(your_out[2],.S3(your_out[3],.S4(your_out[4],.S5(your_out[5] S6.(your_out[6]), S7.(your_out[7], .Cout(Cout),.Cin(Cin), .A0(newa[0]),.A1(newa[1]),.A2(newa[2]),.A3(newa[3]),.A4(newa[4]),.A5(newa[5]), .A6(newa[6]),.A7(newa[7]), .B0(newb[0]),.B1(newb[1]),.B2(newb[2]),.B3(newb[3]),.B4(newb[4]), .B5(newb[5]),.B6(newb[6]),.B7(newb[7])); endmodule I also get in error saying: Error (10170): Verilog HDL syntax error at your_ALU_mux.v(66) near text "if"; expecting "endmodule" And the it brings me to my first if statement. Is this the wrong way of going about creating wires and them using them?

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  • Verilog errors during synthesis

    - by chester.boo
    Here is the code in question: http://pastebin.com/smqUNpdt When I do a syntax check, everything is okay. But when I try to synthesize with XST I get the following errors: ERROR:Xst:870 - "fibonacci.v" line 42: Can not simplify operator DIV. ERROR:Xst:899 - "fibonacci.v" line 29: The logic for <out> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 30: The logic for <ratio> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 36: The logic for <nextstate> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 37: The logic for <previousstate> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 38: The logic for <presentstate> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 39: The logic for <fib_number_cnt> does not match a known FF or Latch template.

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  • Verilog Posedge Problem

    - by Cenoc
    I'm having the following problem; I have a clk at 50MHz, but I want something else to run with a posedge signal whenever ready, but for some reason it always goes at the 50MHz, although I explicitly write otherwise, do you guys have any suggestions?

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  • how to store data in ram in verilog

    - by anum
    i am having a bit stream of 128 bits @ each posedge of clk,i.e.total 10 bit streams each of length 128 bits. i want to divide the 128 bit stream into 8, 8 bits n hve to store them in a ram / memory of width 8 bits. i did it by assigning 8, 8 bits to wires of size 8 bit.in this way there are 16 wires. and i am using dual port ram...wen i cal module of memory in stimulus.i don know how to give input....as i am hving 16 different wires naming from k1 to k16. **codeeee** // this is stimulus file module final_stim; reg [7:0] in,in_data; reg clk,rst_n,rd,wr,rd_data,wr_data; wire [7:0] out,out_wr, ouut; wire[7:0] d; integer i; //wire[7:0] xor_out; reg kld,f; reg [127:0]key; wire [127:0] key_expand; wire [7:0]out_data; reg [7:0] k; //wire [7:0] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16; wire [7:0] out_data1; **//key_expand is da output which is giving 10 streams of size 128 bits.** assign k1=key_expand[127:120]; assign k2=key_expand[119:112]; assign k3=key_expand[111:104]; assign k4=key_expand[103:96]; assign k5=key_expand[95:88]; assign k6=key_expand[87:80]; assign k7=key_expand[79:72]; assign k8=key_expand[71:64]; assign k9=key_expand[63:56]; assign k10=key_expand[55:48]; assign k11=key_expand[47:40]; assign k12=key_expand[39:32]; assign k13=key_expand[31:24]; assign k14=key_expand[23:16]; assign k15=key_expand[15:8]; assign k16=key_expand[7:0]; **// then the module of memory is instanciated. //here k1 is sent as input.but i don know how to save the other values of k. //i tried to use for loop but it dint help** memory m1(clk,rst_n,rd, wr,k1,out_data1); aes_sbox b(out,d); initial begin clk=1'b1; rst_n=1'b0; #20 rst_n = 1; //rd=1'b1; wr_data=1'b1; in=8'hd4; #20 //rst_n=1'b1; in=8'h27; rd_data=1'b0; wr_data=1'b1; #20 in=8'h11; rd_data=1'b0; wr_data=1'b1; #20 in=8'hae; rd_data=1'b0; wr_data=1'b1; #20 in=8'he0; rd_data=1'b0; wr_data=1'b1; #20 in=8'hbf; rd_data=1'b0; wr_data=1'b1; #20 in=8'h98; rd_data=1'b0; wr_data=1'b1; #20 in=8'hf1; rd_data=1'b0; wr_data=1'b1; #20 in=8'hb8; rd_data=1'b0; wr_data=1'b1; #20 in=8'hb4; rd_data=1'b0; wr_data=1'b1; #20 in=8'h5d; rd_data=1'b0; wr_data=1'b1; #20 in=8'he5; rd_data=1'b0; wr_data=1'b1; #20 in=8'h1e; rd_data=1'b0; wr_data=1'b1; #20 in=8'h41; rd_data=1'b0; wr_data=1'b1; #20 in=8'h52; rd_data=1'b0; wr_data=1'b1; #20 in=8'h30; rd_data=1'b0; wr_data=1'b1; #20 wr_data=1'b0; #380 rd_data=1'b1; #320 rd_data = 1'b0; /////////////// #10 kld = 1'b1; key=128'h 2b7e151628aed2a6abf7158809cf4f3c; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b0; #10 wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 kld = 1'b0; key = 128'h 2b7e151628aed2a6abf7158809cf4f3c; wr = 1'b1; rd = 1'b1; #20 wr = 1'b0; #20 rd = 1'b1; #4880 f=1'b1; ///////////////////////////////////////////////// // out_data[i] end /*always@(*) begin while(i) mem[i]^mem1[i] ; i<=16; break; end*/ always #10 clk=~clk; always@(posedge clk) begin //$monitor($time," out_wr=%h,out_rd=%h\n ",out_wr,out); #10000 $stop; end endmodule

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  • Exporting tasks to 'C using DPI

    - by Alphaneo
    I have an verilog based test-bench, interfaced to 'C source using DPI. Now using DPI I am planning to write my whole firmware. To do this I need 3 things Register Read Register Write Interrupt handler As I understand, register reads and writes are tasks that I need to export from the RTL test-bench. And Interrupt handler (I implemented by importing a function from 'C). I checked most the cadence documentation and found no useful hints. I have also registered with cadence users community but it seems that I cannot ask question till they approve my registration. Just in case someone is aware of this, would appreciate their help.

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  • output not updating until next clock cycle

    - by EquinoX
    I have the code module below always @(posedge Clk) begin ForwardA = 0; ForwardB = 0; //EX Hazard if (EXMEMRegWrite == 1) begin if (EXMEMrd != 0) if (EXMEMrd == IDEXrs) ForwardA = 2'b10; if (EXMEMrd == IDEXrt && IDEXTest == 0) ForwardB = 2'b10; end //MEM Hazard if (MEMWBRegWrite == 1) begin if (MEMWBrd != 0) begin if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs))) if (MEMWBrd == IDEXrs) ForwardA = 2'b01; if (IDEXTest == 0) begin if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt))) if (MEMWBrd == IDEXrt) ForwardB = 2'b01; end end end end The problem is that the output, which is ForwardA and ForwardB is not updated not on the rising clock edge rather than on the next rising clock edge... why is this?? How do I resolve so that the output is updated on the same positive rising clock edge? Here's what I mean: ForwardA is updated with 2 on the next rising clock edge and not on the same rising clock edge

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  • Should you remove all warnings in your Verilog or VHDL design? Wh or why not?

    - by Brian Carlton
    In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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  • Should you remove all warnings in your Verilog or VHDL design? Why or why not?

    - by Brian Carlton
    In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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  • Run verilog on Mac

    - by Gabe
    I need to simulate verilog on my Macbook Pro for school. I've tried downloading, configuring, and installing icarus and veriwell. The make test works for icarus, but not for veriwell, neither of them are recognized by the terminal. The command I'm using is: iverilog hello.vl and veriwell hello.vl Terminal claims that neither of these commands exist... I'm very new at configuring tools with the terminal, but I think the issue is just USING the program afterwards. Any ideas?

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  • How to 'assign' a value to an output reg in Verilog?

    - by Rafael Almeida
    ( insert really basic question disclaimer here ) More specifically, I have the following declaration: output reg icache_ram_rw And in some point of the code I need to put the zero value in this reg. Here's what I've tried and the outcomes: assign icache_ram_rw = 1'b0; ( declarative lvalue or port sink reg icache_ram_rw must be a wire ) icache_ram_rw <= 1'b0; ( instance gate/name for type "icache_ram_rw" expected - <= read ) How do I do it after all?!

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  • How can I rewrite Verilog code to remove extra reg?

    - by EquinoX
    How can I rewrite the code below so that I don't need to have an extra reg mul. I just wanted to take the 32 bits of the resulting 32 * 32 bit multiplication and put it into Result input signed[31:0] Reg1; input signed[31:0] Reg2; output[31:0] Result; reg signed[31:0] Result; reg[63:0] mul; mul = Reg1 * Reg2; Result = mul[31:0];

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  • How to write a linter?

    - by jbdavid
    In my day job I, and others on my team write a lot of hardware models in Verilog-AMS, a language supported primarily by commercial vendors and a few opensource simulator projects. One thing that would make supporting each others code more helpful would be a LINTER that would check our code for common problems and assist with enforcing a shared code formatting style. I of course want to be able to add my own rules and, after I prove their utility to myself, promote them to the rest of the team.. I don't mind doing the work that has to be done, but of course also want to leverage the work of other existing projects. Does having the allowed language syntax in a yacc or bison format give me a leg up? or should I just suck each language statement into a perl string, and use pattern matching to find the things I don't like? (most syntax and compilation errors are easily caught by the commercial tools.. but we have some of our own extentions.)

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  • AES BYTE SYSTOLIC ARCHITECTURE.

    - by anum
    we are implementing AES BYTE SYSTOLIC ARCHITECTURE. CODE:- module key_expansion(kld,clk,key,key_expand,en); input kld,clk,en; input [127:0] key; wire [31:0] w0,w1,w2,w3; output [127:0] key_expand; reg[127:0] key_expand; reg [31:0] w[3:0]; reg [3:0] ctr; //reg [31:0] w0,w1,w2,w3; wire [31:0] c0,c1,c2,c3; wire [31:0] tmp_w; wire [31:0] subword; wire [31:0] rcon; assign w0 = w[0]; assign w1 = w[1]; assign w2 = w[2]; assign w3 = w[3]; //always @(posedge clk) always @(posedge clk) begin w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon; end always @(posedge clk) begin w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon; end always @(posedge clk) begin w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon; end always @(posedge clk) begin w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon; end assign tmp_w = w[3]; aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24])); aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16])); aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08])); aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00])); aes_rcon r0( .clk(clk), .kld(kld), .out_rcon(rcon)); //assign key_expand={w0,w1,w2,w3}; //assign key_expand={w0,w1,w2,w3}; always@(posedge clk) begin if (!en) begin ctr<=0; end else if (|ctr) begin key_expand<=0; ctr<=(ctr+1)%16; end else if (!(|ctr)) begin key_expand<={w0,w1,w2,w3}; ctr<=(ctr+1)%16; end end endmodule problem:verilog code has been attached THE BASIC problem is that we want to generate a new key after 16 clock cycles.whereas initially it would generate a new key every posedge of clock.in order to stop the value from being assigned to w[0] w[1] w[2] w[3] we implemented an enable counter logic as under.it has enabled us to give output in key_expand after 16 cycles but the value of required keys has bin changed.because the key_expand takes up the latest value from w[0],w[1],w[2],w[3] where as we require the first value generated.. we should block the value to be assigned to w[0] to w[3] somehow ..but we are stuck.plz help.

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