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  • Organizations &amp; Architecture UNISA Studies &ndash; Chap 7

    - by MarkPearl
    Learning Outcomes Name different device categories Discuss the functions and structure of I/.O modules Describe the principles of Programmed I/O Describe the principles of Interrupt-driven I/O Describe the principles of DMA Discuss the evolution characteristic of I/O channels Describe different types of I/O interface Explain the principles of point-to-point and multipoint configurations Discuss the way in which a FireWire serial bus functions Discuss the principles of InfiniBand architecture External Devices An external device attaches to the computer by a link to an I/O module. The link is used to exchange control, status, and data between the I/O module and the external device. External devices can be classified into 3 categories… Human readable – e.g. video display Machine readable – e.g. magnetic disk Communications – e.g. wifi card I/O Modules An I/O module has two major functions… Interface to the processor and memory via the system bus or central switch Interface to one or more peripheral devices by tailored data links Module Functions The major functions or requirements for an I/O module fall into the following categories… Control and timing Processor communication Device communication Data buffering Error detection I/O function includes a control and timing requirement, to coordinate the flow of traffic between internal resources and external devices. Processor communication involves the following… Command decoding Data Status reporting Address recognition The I/O device must be able to perform device communication. This communication involves commands, status information, and data. An essential task of an I/O module is data buffering due to the relative slow speeds of most external devices. An I/O module is often responsible for error detection and for subsequently reporting errors to the processor. I/O Module Structure An I/O module functions to allow the processor to view a wide range of devices in a simple minded way. The I/O module may hide the details of timing, formats, and the electro mechanics of an external device so that the processor can function in terms of simple reads and write commands. An I/O channel/processor is an I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor. There are 3 techniques are possible for I/O operations Programmed I/O Interrupt[t I/O DMA Access Programmed I/O When a processor is executing a program and encounters an instruction relating to I/O it executes that instruction by issuing a command to the appropriate I/O module. With programmed I/O, the I/O module will perform the requested action and then set the appropriate bits in the I/O status register. The I/O module takes no further actions to alert the processor. I/O Commands To execute an I/O related instruction, the processor issues an address, specifying the particular I/O module and external device, and an I/O command. There are four types of I/O commands that an I/O module may receive when it is addressed by a processor… Control – used to activate a peripheral and tell it what to do Test – Used to test various status conditions associated with an I/O module and its peripherals Read – Causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer Write – Causes the I/O module to take an item of data form the data bus and subsequently transmit that data item to the peripheral The main disadvantage of this technique is it is a time consuming process that keeps the processor busy needlessly I/O Instructions With programmed I/O there is a close correspondence between the I/O related instructions that the processor fetches from memory and the I/O commands that the processor issues to an I/O module to execute the instructions. Typically there will be many I/O devices connected through I/O modules to the system – each device is given a unique identifier or address – when the processor issues an I/O command, the command contains the address of the address of the desired device, thus each I/O module must interpret the address lines to determine if the command is for itself. When the processor, main memory and I/O share a common bus, two modes of addressing are possible… Memory mapped I/O Isolated I/O (for a detailed explanation read page 245 of book) The advantage of memory mapped I/O over isolated I/O is that it has a large repertoire of instructions that can be used, allowing more efficient programming. The disadvantage of memory mapped I/O over isolated I/O is that valuable memory address space is sued up. Interrupts driven I/O Interrupt driven I/O works as follows… The processor issues an I/O command to a module and then goes on to do some other useful work The I/O module will then interrupts the processor to request service when is is ready to exchange data with the processor The processor then executes the data transfer and then resumes its former processing Interrupt Processing The occurrence of an interrupt triggers a number of events, both in the processor hardware and in software. When an I/O device completes an I/O operations the following sequence of hardware events occurs… The device issues an interrupt signal to the processor The processor finishes execution of the current instruction before responding to the interrupt The processor tests for an interrupt – determines that there is one – and sends an acknowledgement signal to the device that issues the interrupt. The acknowledgement allows the device to remove its interrupt signal The processor now needs to prepare to transfer control to the interrupt routine. To begin, it needs to save information needed to resume the current program at the point of interrupt. The minimum information required is the status of the processor and the location of the next instruction to be executed. The processor now loads the program counter with the entry location of the interrupt-handling program that will respond to this interrupt. It also saves the values of the process registers because the Interrupt operation may modify these The interrupt handler processes the interrupt – this includes examination of status information relating to the I/O operation or other event that caused an interrupt When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers Finally, the PSW and program counter values from the stack are restored. Design Issues Two design issues arise in implementing interrupt I/O Because there will be multiple I/O modules, how does the processor determine which device issued the interrupt? If multiple interrupts have occurred, how does the processor decide which one to process? Addressing device recognition, 4 general categories of techniques are in common use… Multiple interrupt lines Software poll Daisy chain Bus arbitration For a detailed explanation of these approaches read page 250 of the textbook. Interrupt driven I/O while more efficient than simple programmed I/O still requires the active intervention of the processor to transfer data between memory and an I/O module, and any data transfer must traverse a path through the processor. Thus is suffers from two inherent drawbacks… The I/O transfer rate is limited by the speed with which the processor can test and service a device The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer Direct Memory Access When large volumes of data are to be moved, an efficient technique is direct memory access (DMA) DMA Function DMA involves an additional module on the system bus. The DMA module is capable of mimicking the processor and taking over control of the system from the processor. It needs to do this to transfer data to and from memory over the system bus. DMA must the bus only when the processor does not need it, or it must force the processor to suspend operation temporarily (most common – referred to as cycle stealing). When the processor wishes to read or write a block of data, it issues a command to the DMA module by sending to the DMA module the following information… Whether a read or write is requested using the read or write control line between the processor and the DMA module The address of the I/O device involved, communicated on the data lines The starting location in memory to read from or write to, communicated on the data lines and stored by the DMA module in its address register The number of words to be read or written, communicated via the data lines and stored in the data count register The processor then continues with other work, it delegates the I/O operation to the DMA module which transfers the entire block of data, one word at a time, directly to or from memory without going through the processor. When the transfer is complete, the DMA module sends an interrupt signal to the processor, this the processor is involved only at the beginning and end of the transfer. I/O Channels and Processors Characteristics of I/O Channels As one proceeds along the evolutionary path, more and more of the I/O function is performed without CPU involvement. The I/O channel represents an extension of the DMA concept. An I/O channel ahs the ability to execute I/O instructions, which gives it complete control over I/O operations. In a computer system with such devices, the CPU does not execute I/O instructions – such instructions are stored in main memory to be executed by a special purpose processor in the I/O channel itself. Two types of I/O channels are common A selector channel controls multiple high-speed devices. A multiplexor channel can handle I/O with multiple characters as fast as possible to multiple devices. The external interface: FireWire and InfiniBand Types of Interfaces One major characteristic of the interface is whether it is serial or parallel parallel interface – there are multiple lines connecting the I/O module and the peripheral, and multiple bits are transferred simultaneously serial interface – there is only one line used to transmit data, and bits must be transmitted one at a time With new generation serial interfaces, parallel interfaces are becoming less common. In either case, the I/O module must engage in a dialogue with the peripheral. In general terms the dialog may look as follows… The I/O module sends a control signal requesting permission to send data The peripheral acknowledges the request The I/O module transfers data The peripheral acknowledges receipt of data For a detailed explanation of FireWire and InfiniBand technology read page 264 – 270 of the textbook

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  • ARMv6 FIQ, acknowledge interrupt

    - by fastmonkeywheels
    I'm working with an i.mx35 armv6 core processor. I have Interrupt 62 configured as a FIQ with my handler installed and being called. My handler at the moment just toggles an output pin so I can test latency with a scope. With the code below, once I trigger the FIQ it continues forever as fast as it can, apparently not being acknowledged. I'm triggering the FIQ by means of the Interrupt Force Register so I'm assured that the source isn't triggering it this fast. If I disable Interrupt 62 in the AVIC in my FIQ routine the interrupt only triggers once. I have read the sections on the VIC Port in the ARM1136JF-S and ARM1136J-S Technical Reference Manual and it covers proper exit procedure. I'm only having one FIQ handler so I have no need to branch. The line that I don't understand is: STR R0, [R8,#AckFinished] I'm not sure what AckFinished is supposed to be or what this command is supposed to do. My FIQ handler is below: ldr r9, IOMUX_ADDR12 ldr r8, [r9] orr r8, #0x08 @ top LED str r8,[r9] @turn on LED bic r8, #0x08 @ top LED str r8,[r9] @turn off LED subs pc, r14, #4 IOMUX_ADDR12: .word 0xFC2A4000 @remapped IOMUX addr My handler returns just fine and normal system operation resumes if I disable it after the first go, otherwise it triggers constantly and the system appears to hang. Do you think my assumption is right that the core isn't acknowledging the AVIC or could there be another cause of this FIQ triggering?

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  • AMD Opteron BSOD - A clock interrupt was not received on a secondary processor within the allocatio

    - by laurens
    On one of our servers we got an -for me new- BSOD with the error message: "A clock interrupt was not received on a secondary processor within the allocation time interval" The server's specs: HP XW9400 2x Dual-Core AMD Opeteron 2224 SE 3,20Ghz (4CPUs) 16GB HP ECC RAM Windows 2008 R2 Enterprise 64bit Nvidia Quadro 4xxx graphics (?) Sounds familiar to someone ? Thanks in advance

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  • How to interrupt software raid resync?

    - by Adam5
    I want to interrupt a running resync operation on an ubuntu 10.04 software raid. (This is the regular scheduled compare resync) How to stop it while it is running? Another raid array is "resync pending", I want a complete stop of all resyncing. [Edit: "sudo kill -9 1010" doesn't do anything, 1010 is the PID of the md2_resync process] I would also like to know how I can control the intervals between resyncs and the remainig time till the next one.

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  • ArrayBlockingQueue - How to "interrupt" a thread that is wating on .take() method

    - by bernhard
    I use an ArrayBlockingQueue in my code. Clients will wait untill an element becomes available: myBlockingQueue.take(); How can I "shutdown" my service in case no elements are present in the queue and the take() ist wating indefenitely for an element to become available? This method throws an InterruptedException. My question is, how can I "evoke" an Interrupted Exception so that take() will quit? (I also tought about notify(), but it seems I doesnt help here..) I know I could insert an special "EOF/QUIT" marker Element but is this really the only solution? UPDATE (regarding the comment, that points to another question with two solutions: one mentioned above using a "Poisoning Pill Object" and the second one is Thread.interrupt(): The myBlockingQueue.take() is used NOT in a Thread (extending Thread) but rather implements Runnable. It seems a Runnable does not provide the .interrupt() method? How could I interrupt the Runnable? Million Thanks Bernhard

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  • How is the RIP loaded when an interrupt arrives in an IA-32e 64-bit IDT Gate Descriptor?

    - by Vern
    I need some help with the programming of an IA-32e Interrupt Descriptor as I'm pretty new to it. I don't think I quite understand how the RIP is loaded when an Interrupt arrives. There is a Segment Selector in Intel's 64-bit IDT Gate Descriptor. However, from my understanding across the 5 part Intel manuals, the Linear Address of the Interrupt Handler is loaded into RIP from the 64-bit offset specified in the IDT Gate Descriptor. The only use of the segment selector is to check: if there is a change in privilege levels the Interrupt Handler is truly pointing to a code segment My questions are: Is RIP taken from the 64-bit offset only? Or is RIP = offset(sign extended to 64-bits) + segment selector base? Is the base address pointed to by the segment selector in the IDT Gate Descriptor ignored? Or does it have a use?

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  • Why is my masm32 program crashing whenever I try using interrupts?

    - by incrediman
    Here's the code: .386 ;target for maximum compatibility .model small,stdcall ;model .code main: int 20h END main Result: http://img705.imageshack.us/img705/3738/resultom.png "test.exe has stopped working" - always right when it reaches the interrupt. This is the interrupt I'm trying to use. It should simply exit the program. Others I've tried include character input/output, etc.. Nothing works. I'm on windows 7, using masm32 with the WinAsm IDE. There are so many cool things it seems I should be able to do with interrupts... however, it crashes whenever I try to use an interrupt - always the same way. This seems related and possibly useful: http://stackoverflow.com/questions/1414260/dos-interrupt-in-masm-x86-assembly-crashing ...but I haven't really been able to figure anything out from it. Any suggestions?

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  • How are interrupts handled by dual processor machines?

    - by jeffD
    I have an idea of how interrupts are handled by a dual core CPU. I was wondering about how interrupt handling is implemented on a board with more than one physical processor. Is any of the interrupt responsibility determined by the physical board's configuration? Each processor must be able to handle some types of interrupts, like disk I/O. Unless there is some circuitry to manage and dispatch interrupts to the appropriate processor? My guess is that the scheme must be processor neutral, so that any processor and core can run the interrupt handler. If a core is waiting on a disk read, will that core be the one to run the interrupt handler when the disk is ready?

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  • Interrupting a thread from inside a runnable class? (java)

    - by kyeana
    I am trying to set up a method inside a class that implements the runnable interface that will set the interrupt status of that class. The reason i want to be able to do it from inside the class is there is some other clean up stuff that i need to take care of as well, and i would like to be able to do it all by calling one method instead of calling, for example: Gui gui = new Gui() // class that implements runnable Thread guiThread = new Thread(gui, "gui thread"); guiThread.start() ... ... guiThread.interrupt(); gui.cancel(); Currently my cancel code looks like this, however it isn't correctly setting the interrupt status of this thread. public void cancel() { Thread.currentThread().interrupt(); // other clean up code here. } Any advice on if/how i could get this working? Thanks. EDIT: I when i tried to get the cancel working, i commented out the guiThread.interrupt(), so that i wasn't just setting the status the reseting the status.

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  • How to interrupt software raid resync?

    - by Adam5
    I want to interrupt a running resync operation on a debian squeeze software raid. (This is the regular scheduled compare resync. The raid array is still clean in such a case. Do not confuse this with a rebuild after a disk failed and was replaced.) How to stop this scheduled resync operation while it is running? Another raid array is "resync pending", because they all get checked on the same day (sunday night) one after another. I want a complete stop of this sunday night resyncing. [Edit: sudo kill -9 1010 doesn't stop it, 1010 is the PID of the md2_resync process] I would also like to know how I can control the intervals between resyncs and the remainig time till the next one. [Edit2: What I did now was to make the resync go very slow, so it does not disturb anymore: sudo sysctl -w dev.raid.speed_limit_max=1000 taken from http://www.cyberciti.biz/tips/linux-raid-increase-resync-rebuild-speed.html During the night I will set it back to a high value, so the resync can terminate. This workaround is fine for most situations, nonetheless it would be interesting to know if what I asked is possible. For example it does not seem to be possible to grow an array, while it is resyncing or resyncing "pending"]

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  • Python: Catching / blocking SIGINT during system call

    - by danben
    I've written a web crawler that I'd like to be able to stop via the keyboard. I don't want the program to die when I interrupt it; it needs to flush its data to disk first. I also don't want to catch KeyboardInterruptedException, because the persistent data could be in an inconsistent state. My current solution is to define a signal handler that catches SIGINT and sets a flag; each iteration of the main loop checks this flag before processing the next url. However, I've found that if the system happens to be executing socket.recv() when I send the interrupt, I get this: ^C Interrupted; stopping... // indicates my interrupt handler ran Traceback (most recent call last): File "crawler_test.py", line 154, in <module> main() ... File "/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/socket.py", line 397, in readline data = recv(1) socket.error: [Errno 4] Interrupted system call and the process exits completely. Why does this happen? Is there a way I can prevent the interrupt from affecting the system call?

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  • Catching / blocking SIGINT during system call

    - by danben
    I've written a web crawler that I'd like to be able to stop via the keyboard. I don't want the program to die when I interrupt it; it needs to flush its data to disk first. I also don't want to catch KeyboardInterruptedException, because the persistent data could be in an inconsistent state. My current solution is to define a signal handler that catches SIGINT and sets a flag; each iteration of the main loop checks this flag before processing the next url. However, I've found that if the system happens to be executing socket.recv() when I send the interrupt, I get this: ^C Interrupted; stopping... // indicates my interrupt handler ran Traceback (most recent call last): File "crawler_test.py", line 154, in <module> main() ... File "/Library/Frameworks/Python.framework/Versions/2.6/lib/python2.6/socket.py", line 397, in readline data = recv(1) socket.error: [Errno 4] Interrupted system call and the process exits completely. Why does this happen? Is there a way I can prevent the interrupt from affecting the system call?

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  • Who interrupts my thread?

    - by Thirler
    I understand what an InterruptedException does and why it is thrown. However in my application I get it when waiting for SwingUtilities.invokeAndWait() on a thread that is only known by my application, and my application never class Thread.interrupt() on any thread, also it never passes the reference of the thread on to anyone. So my question is: Who interrupts my thread? Is there any way to tell? Is there a reason why the InterruptedException doesn't contain the name of the Thread that requests the interrupt? I read that it could be a framework or library that does this, we use the following, but I can't think of reason for them to interrupt my thread: Hibernate Spring Log4J Mysql connector

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  • Any techniques to interrupt, kill, or otherwise unwind (releasing synchronization locks) a single de

    - by gojomo
    I have a long-running process where, due to a bug, a trivial/expendable thread is deadlocked with a thread which I would like to continue, so that it can perform some final reporting that would be hard to reproduce in another way. Of course, fixing the bug for future runs is the proper ultimate resolution. Of course, any such forced interrupt/kill/stop of any thread is inherently unsafe and likely to cause other unpredictable inconsistencies. (I'm familiar with all the standard warnings and the reasons for them.) But still, since the only alternative is to kill the JVM process and go through a more lengthy procedure which would result in a less-complete final report, messy/deprecated/dangerous/risky/one-time techniques are exactly what I'd like to try. The JVM is Sun's 1.6.0_16 64-bit on Ubuntu, and the expendable thread is waiting-to-lock an object monitor. Can an OS signal directed to an exact thread create an InterruptedException in the expendable thread? Could attaching with gdb, and directly tampering with JVM data or calling JVM procedures allow a forced-release of the object monitor held by the expendable thread? Would a Thread.interrupt() from another thread generate a InterruptedException from the waiting-to-lock frame? (With some effort, I can inject an arbitrary beanshell script into the running system.) Can the deprecated Thread.stop() be sent via JMX or any other remote-injection method? Any ideas appreciated, the more 'dangerous', the better! And, if your suggestion has worked in personal experience in a similar situation, the best!

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  • Very High Interrupt CPU usage in Win2k3 VM on vSphere

    - by Darragh
    Hi, I've been testing some software in a server virtual environment and I've noticed I get a huge amount of CPU usage on the Interrupts process. My question is, how does this relate to the virtual hardware platform as the rate is allot lower in a real system. Some how the hypervizor scheduler works hard to over come this problem but not as well as on real hardware does. Obvious things are high I/O and disk access but this application mostly just sits and works in memory allot. If anyone has experienced the same, please let me know. thanks in advance Screenshot: Process Explorer

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  • How to interrupt stuck bash tab completion?

    - by codeape
    Case: A Windows share mounted using samba over a flaky VPN connection (sometimes very slow, sometimes it drops) When doing tab-completion on filenames, my bash shell can freeze up if the VPN is slow or dropped when I am attempting the tab completion. Example: $ cp myfile.zip /mnt/winbox-c/Progr<tab> key pressed here Is there a bash key I can press to get bash out of its hung state when something like this happens?

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  • Do USB interrupt transfers guarantee order?

    - by ulidtko
    I've found in the fairly awesome book titled "USB in a NutShell" that interrupt transfers provide reliable delivery (via error detection and automatic retry). But I wonder, does that guarantee that transfers will not be swapped in order someday? As far as the bus is serial, my guess is that yes, reordering should never occur. But I'm not really much into this, so having doubts. Could somebody clarify?

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  • NNTP & Socket - How to interrupt?

    - by Cosmo
    Hi. I'm sending a message to a NNTP server in order to fetch an article's body. I don't want to wait for the answer to complete, cause I only need the first 3 lines from the body. How can I interrupt the transfer and move on to the next article? Now when I request another's article message body, I still get data from the previous one. The only way that worked for me, was to close the stream and reopen it. In my opinion this is a little bit hardcore, cause I have to login to the server every time I need a new file. Any help would be appreciated. Kind Regards.

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  • Interrupt an Http Request blocked in read() on Android

    - by twk
    Using the Apache Http stack on Android, I'm trying to force a thread out of a call to read. This is what the stack looks like: OSNetworkSystem.receiveStreamImpl(FileDescriptor, byte[], int, int, int) line: not available [native method] OSNetworkSystem.receiveStream(FileDescriptor, byte[], int, int, int) line: 478 PlainSocketImpl.read(byte[], int, int) line: 565 SocketInputStream.read(byte[], int, int) line: 87 SocketInputBuffer(AbstractSessionInputBuffer).fillBuffer() line: 103 SocketInputBuffer(AbstractSessionInputBuffer).read(byte[], int, int) line: 134 IdentityInputStream.read(byte[], int, int) line: 86 EofSensorInputStream.read(byte[], int, int) line: 159 Fetcher.readStream() line: 89 I've tried InputStream.close(), Thread.Interrupt(), and HttpUriRequest.abort(), without any success. Any ideas? I'm also open to some kind of non-blocking IO, but I don't see any way to do that with the HttpUriRequest object. Thanks!

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  • Interrupt a thread in DatagramSocket.receive

    - by SEK
    I'm building an application that listens on both TCP and UDP, and I've run into some trouble with my shutdown mechanism. When I call Thread.interrupt() on each of the listening threads, the TCP thread is interrupted from listening, whereas the UDP listener isn't. To be specific, the TCP thread uses Socket.accept(), which simply returns (without actually connecting). Whereas the UDP thread uses DatagramSocket.receive, and doesn't exit that method. Is this an issue in my JRE, my OS, or should I just switch to (Datagram)Socket.close()?

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  • Passing parameters between interrupt handlers on a Cortex-M3 ...

    - by Captain NedD
    I'm building a light kernel for a Cortex-M3. From a high priority interrupt I'd like to invoke some code to run in a lower priority interrupt and pass some parameters along. I don't want to use a queue to post work to the lower priority interrupt. I just have a buffer and size to pass to it. In the proramming manual it says that the SVC interrupt handler is synchronous which presumably means that if you invoke it from an interrupt that's a lower priority than SVC's handler it gets called immediately (the upshot of this being that you can pass parameters to it as though it were a function call (a little like the BIOS calls in MS-DOS)). I'd like to do it the other way: passing parameters from a high priority interrupt to a lower priority one (at the moment I'm doing it by leaving the parameters in a fixed location in memory). What's the best way to do this (if at all possible)? Thanks,

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  • Count seconds and minutes with MCU timer/interrupt?

    - by arynhard
    I am trying to figure out how to create a timer for my C8051F020 MCU. The following code uses the value passed to init_Timer2() with the following formula: 65535-(0.1 / (12/2000000)=48868. I set up the timer to count every time it executes and for every 10 counts, count one second. This is based on the above formula. 48868 when passed to init_Timer2 will produce a 0.1 second delay. It would take ten of them per second. However, when I test the timer it is a little fast. At ten seconds the timer reports 11 seconds, at 20 seconds the timer reports 22 seconds. I would like to get as close to a perfect second as I can. Here is my code: #include <compiler_defs.h> #include <C8051F020_defs.h> void init_Clock(void); void init_Watchdog(void); void init_Ports(void); void init_Timer2(unsigned int counts); void start_Timer2(void); void timer2_ISR(void); unsigned int timer2_Count; unsigned int seconds; unsigned int minutes; int main(void) { init_Clock(); init_Watchdog(); init_Ports(); start_Timer2(); P5 &= 0xFF; while (1); } //============================================================= //Functions //============================================================= void init_Clock(void) { OSCICN = 0x04; //2Mhz //OSCICN = 0x07; //16Mhz } void init_Watchdog(void) { //Disable watchdog timer WDTCN = 0xDE; WDTCN = 0xAD; } void init_Ports(void) { XBR0 = 0x00; XBR1 = 0x00; XBR2 = 0x40; P0 = 0x00; P0MDOUT = 0x00; P5 = 0x00; //Set P5 to 1111 P74OUT = 0x08; //Set P5 4 - 7 (LEDs) to push pull (Output) } void init_Timer2(unsigned int counts) { CKCON = 0x00; //Set all timers to system clock divided by 12 T2CON = 0x00; //Set timer 2 to timer mode RCAP2 = counts; T2 = 0xFFFF; //655535 IE |= 0x20; //Enable timer 2 T2CON |= 0x04; //Start timer 2 } void start_Timer2(void) { EA = 0; init_Timer2(48868); EA = 1; } void timer2_ISR(void) interrupt 5 { T2CON &= ~(0x80); P5 ^= 0xF0; timer2_Count++; if(timer2_Count % 10 == 0) { seconds++; } if(seconds % 60 == 0 && seconds != 0) { minutes++; } }

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  • Sd card bigger than 2gb is not recognized in ubuntu 12.04

    - by dex1
    When I insert a card up to 2gb it is immediately seen by the system but if try it with bigger one it's not seen. I presume the issue is not due to the card reader itself as it reads all cards under windows 7 but due to linux driver. I could see some people having similar issues but no solution. Any help appreciated. GParted doesnt see cards bigger than 2gb. After insertion small card ubuntu@ubuntu:~$ dmesg [10169.384481] mmc0: new SD card at address a95c [10169.384870] mmcblk0: mmc0:a95c SD016 14.0 MiB [10169.386715] mmcblk0: p1 everything worked fine then I removed the small one and put 8gb, waited for 2min [10295.736422] mmc0: card a95c removed [10362.448383] sdhci: Switching to 1.8V signalling voltage failed, retrying with S18R set to 0 [10372.480076] mmc0: Timeout waiting for hardware interrupt. [10382.496146] mmc0: Timeout waiting for hardware interrupt. [10392.512149] mmc0: Timeout waiting for hardware interrupt. [10402.528145] mmc0: Timeout waiting for hardware interrupt. [10402.529267] mmc0: error -110 whilst initialising SD card [10402.748807] sdhci: Switching to 1.8V signalling voltage failed, retrying with S18R set to 0 [10412.768063] mmc0: Timeout waiting for hardware interrupt. [10422.784051] mmc0: Timeout waiting for hardware interrupt. [10432.800076] mmc0: Timeout waiting for hardware interrupt. [10442.816067] mmc0: Timeout waiting for hardware interrupt. [10442.817165] mmc0: error -110 whilst initialising SD card [10443.040805] sdhci: Switching to 1.8V signalling voltage failed, retrying with S18R set to 0 [10453.056145] mmc0: Timeout waiting for hardware interrupt. [10463.072139] mmc0: Timeout waiting for hardware interrupt. [10473.088050] mmc0: Timeout waiting for hardware interrupt. [10483.104046] mmc0: Timeout waiting for hardware interrupt. [10483.104107] mmc0: error -110 whilst initialising SD card [10483.328960] sdhci: Switching to 1.8V signalling voltage failed, retrying with S18R set to 0 [10493.344144] mmc0: Timeout waiting for hardware interrupt. ubuntu@ubuntu:~$ lspci 00:00.0 Host bridge: Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub (rev 03) 00:02.0 VGA compatible controller: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (primary) (rev 03) 00:02.1 Display controller: Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (secondary) (rev 03) 00:1a.0 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 (rev 03) 00:1a.1 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 (rev 03) 00:1a.7 USB controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 (rev 03) 00:1b.0 Audio device: Intel Corporation 82801H (ICH8 Family) HD Audio Controller (rev 03) 00:1c.0 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 1 (rev 03) 00:1c.3 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 4 (rev 03) 00:1c.4 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 5 (rev 03) 00:1c.5 PCI bridge: Intel Corporation 82801H (ICH8 Family) PCI Express Port 6 (rev 03) 00:1d.0 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 (rev 03) 00:1d.1 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 (rev 03) 00:1d.2 USB controller: Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 (rev 03) 00:1d.7 USB controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev f3) 00:1f.0 ISA bridge: Intel Corporation 82801HM (ICH8M) LPC Interface Controller (rev 03) 00:1f.1 IDE interface: Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) IDE Controller (rev 03) 00:1f.2 SATA controller: Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode] (rev 03) 00:1f.3 SMBus: Intel Corporation 82801H (ICH8 Family) SMBus Controller (rev 03) 07:00.0 Ethernet controller: Marvell Technology Group Ltd. 88E8072 PCI-E Gigabit Ethernet Controller (rev 16) 0a:01.0 FireWire (IEEE 1394): O2 Micro, Inc. Firewire (IEEE 1394) (rev 02) 0a:01.2 SD Host controller: O2 Micro, Inc. Integrated MMC/SD Controller (rev 02) 0a:01.3 Mass storage controller: O2 Micro, Inc. Integrated MS/xD Controller (rev 01) Same cards, same machine (same reader) only different OS(win7) work flawlessly. Some interesting reading I came across but is Chinese for me http://www.mail-archive.com/[email protected]/msg14598.html and another bit http://article.gmane.org/gmane.linux.kernel.mmc/11973/match=sd+card+not+recognized

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  • reading keyboard input without "consuming" it in x86 assembly

    - by Bob
    Ok so here the deal: I have an assignment regarding DOS and interrupts: I need to write a sort of key-logger function that can be called from C code. what it means is a c program would call an assembly function called startlog that would indicate to start logging the keys pressed until a function called endlog is called. the logging should work like this: write the ascii value of any key pressed without disturbing the C code between startlog and endlog, meaning that if the C code also needs to read the input (let's say by scanf, it would work ok). I managed to write the logger by changing the interrupt vector 9th entry (interrupt for keyboard press) to a function I wrote that writes the values to a file, and it works fine. however the C code does not get the input. Basically what i did is read the key pressed using int 21h, however after reading the ascii value it is "consumed" so I need a way to either simulate the key press again or read the value without "consuming" it so next time a key is read it reads the same key. (I described the code in english because it is long and clumsy assembly code)

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