Assign a value to a reg in Verilog

Posted by shen on Stack Overflow See other posts from Stack Overflow or by shen
Published on 2010-04-04T14:38:36Z Indexed on 2010/04/05 13:03 UTC
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verilog

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system-verilog

                for (j=0;j<k;j=j+1) begin:loop2
                    assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]};
                end

row is a register.

It does not work as I am doing it. Can anyone please help me to fix it?

Thank you very much.

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