verilog / systemverilog -- What is the behavior of blocking statements across two always blocks?
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Published on 2014-06-09T15:20:49Z
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I am wondering about the behavior of the below code. There are two always blocks, one is combinational to calculate the next_state
signal, the other is sequential which will perform some logic and determine whether or not to shutdown the system. It does this by setting the shutdown_now
signal high and then calling state <= next_state
.
My question is if the conditions become true that the shutdown_now
signal is set (during clock cycle n) in a blocking manner before the state <= next_state
line, will the state during clock cycle n+1 be SHUTDOWN
or RUNNING
? In other words, does the shutdown_now = 1'b1
line block across both state machines since the state
signal is dependent on it through the next_state
determination?
enum {IDLE, RUNNING, SHUTDOWN} state, next_state;
logic shutdown_now;
// State machine (combinational)
always_comb begin
case (state)
IDLE: next_state <= RUNNING;
RUNNING: next_state <= shutdown ? SHUTDOWN : RUNNING;
SHUTDOWN: next_state <= SHUTDOWN;
default: next_state <= SHUTDOWN;
endcase
end
// Sequential Behavior
always_ff @ (posedge clk) begin
// Some code here
if (/*some condition) begin
shutdown_now = 1'b0;
end else begin
shutdown_now = 1'b1;
end
state <= next_state;
end
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