How to 'assign' a value to an output reg in Verilog?

Posted by Rafael Almeida on Stack Overflow See other posts from Stack Overflow or by Rafael Almeida
Published on 2009-11-27T16:52:53Z Indexed on 2010/04/12 13:13 UTC
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verilog

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homework

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beginner

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register

( insert really basic question disclaimer here )

More specifically, I have the following declaration:

output reg icache_ram_rw

And in some point of the code I need to put the zero value in this reg. Here's what I've tried and the outcomes:

assign icache_ram_rw = 1'b0;
( declarative lvalue or port sink reg icache_ram_rw must be a wire )

icache_ram_rw <= 1'b0;
( instance gate/name for type "icache_ram_rw" expected - <= read )

How do I do it after all?!

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