Using Regular Expressions for Verilog Port Mapping

Posted by Adam on Stack Overflow See other posts from Stack Overflow or by Adam
Published on 2010-04-16T12:55:23Z Indexed on 2010/04/16 19:53 UTC
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verilog

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regex

So I have a really long port map where I want to replace a bunch of

SignalName[i],

with

.SignalName(SignalName[i]),

I think I can do this easily with regular expressions but I can't for the life of me figure out how. Any ideas?

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Using Regular Expressions for Verilog Port Mapping - Developer IT

Using Regular Expressions for Verilog Port Mapping

verilog

regex

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