Using Regular Expressions for Verilog Port Mapping
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by Adam
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Published on 2010-04-16T12:55:23Z
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2010/04/16
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So I have a really long port map where I want to replace a bunch of
SignalName[i],
with
.SignalName(SignalName[i]),
I think I can do this easily with regular expressions but I can't for the life of me figure out how. Any ideas?
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