we are implementing AES BYTE SYSTOLIC ARCHITECTURE.

CODE:-

module key_expansion(kld,clk,key,key_expand,en); input kld,clk,en; input [127:0] key; wire [31:0] w0,w1,w2,w3; output [127:0] key_expand; reg[127:0] key_expand; reg [31:0] w[3:0]; reg [3:0] ctr; //reg [31:0] w0,w1,w2,w3; wire [31:0] c0,c1,c2,c3;

wire [31:0] tmp_w; wire [31:0] subword; wire [31:0] rcon;

assign w0 = w[0]; assign w1 = w[1]; assign w2 = w[2]; assign w3 = w[3];

//always @(posedge clk)

always @(posedge clk)

begin w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;

end

always @(posedge clk)

begin w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon; end

always @(posedge clk)

begin w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;

end always @(posedge clk)

begin w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon; end

assign tmp_w = w[3];

aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24])); aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16])); aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08])); aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00])); aes_rcon r0( .clk(clk), .kld(kld), .out_rcon(rcon)); //assign key_expand={w0,w1,w2,w3};

//assign key_expand={w0,w1,w2,w3}; always@(posedge clk) begin if (!en) begin ctr<=0;

end else if (|ctr) begin key_expand<=0;

ctr<=(ctr+1)%16; end else if (!(|ctr)) begin key_expand<={w0,w1,w2,w3};

ctr<=(ctr+1)%16; end end

endmodule

problem:verilog code has been attached THE BASIC problem is that we want to generate a new key after 16 clock cycles.whereas initially it would generate a new key every posedge of clock.in order to stop the value from being assigned to w[0] w[1] w[2] w[3] we implemented an enable counter logic as under.it has enabled us to give output in key_expand after 16 cycles but the value of required keys has bin changed.because the key_expand takes up the latest value from w[0],w[1],w[2],w[3] where as we require the first value generated.. we should block the value to be assigned to w[0] to w[3] somehow ..but we are stuck.plz help.