How can I rewrite Verilog code to remove extra reg?

Posted by EquinoX on Stack Overflow See other posts from Stack Overflow or by EquinoX
Published on 2010-04-22T17:32:15Z Indexed on 2010/04/22 21:33 UTC
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verilog

How can I rewrite the code below so that I don't need to have an extra reg mul. I just wanted to take the 32 bits of the resulting 32 * 32 bit multiplication and put it into Result

input signed[31:0] Reg1; 
input signed[31:0] Reg2; 
output[31:0] Result; 
reg signed[31:0] Result; 
reg[63:0] mul; 
mul = Reg1 * Reg2; 
Result = mul[31:0];

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Developer IT

How can I rewrite Verilog code to remove extra reg? - Developer IT

How can I rewrite Verilog code to remove extra reg?

verilog

Related posts about verilog

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