How do I get rid of sensitivity list warning when synthesizing Verilog code?

Posted by EquinoX on Stack Overflow See other posts from Stack Overflow or by EquinoX
Published on 2010-04-21T23:14:08Z Indexed on 2010/04/22 0:53 UTC
Read the original article Hit count: 300

Filed under:

verilog

|

synthesis

I am getting the warning that:

One or more signals are missing in the sensitivity list of always block.

always@(Address)begin
  ReadData = instructMem[Address];
end

How do I get rid of this warning?

© Stack Overflow or respective owner

Related posts about verilog

multiple input wire definiton in verilog?

as seen on Stack Overflow - Search for 'Stack Overflow'
how to create a connection in verilog which interconnects a,b,c,d where a,b,c are inputs.? >>> More
Where can i get Verilog codings?

as seen on Stack Overflow - Search for 'Stack Overflow'
I am doing a project in Verilog, and the project is a low power parallel multiplier. I am going to fed the codings in FPGA kit. I need model Veriog codings. In which site can I get or suggest some good books. >>> More
Assign a value to a reg in Verilog

as seen on Stack Overflow - Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register. It does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. >>> More
assign a value to reg in verilog

as seen on Stack Overflow - Search for 'Stack Overflow'
for (j=0;j<k;j=j+1) begin:loop2 assign row[i+1][j][m+i:0] = {1'b0,row[i][j][m+i-1:0]}; end row is a register, it does not work as I am doing it. Can anyone please help me to fix it? Thank you very much. >>> More
Verilog code simulates but does not run as predicted on FPGA

as seen on Stack Overflow - Search for 'Stack Overflow'
I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin… >>> More

Related posts about synthesis

Video Synthesis - Making waves, patterns, gradients...

as seen on Stack Overflow - Search for 'Stack Overflow'
I'm writing a program to generate some wild visuals. So far I can paint each pixel with a random blue value: for (y = 0; y < YMAX; y++) { for (x = 0; x < XMAX; x++) { b = rand() % 255; setPixelColor(x,y,r,g,b); } } I'd like to do more than just make blue noise, but… >>> More
Video Synthesis - Making waves, pattern, gradients...

as seen on Stack Overflow - Search for 'Stack Overflow'
I'm writing a program to generate some trippy visuals. My code paints each pixel with a random blue value which loops at 0.04 second intervals. for (y = 0; y < 5.5; y += 0.2) { for (x = 0; x < 7.5; x += 0.2) { b = rand() / ((double) RAND_MAX); setPixelColor(x,y,r,g,b); … >>> More
Is there a better approach to speech synthesis than text-to-speech for more natural output? [closed]

as seen on Programmers - Search for 'Programmers'
We've all heard the output of text-to-speech systems, and for anything but very short phrases, it sounds very machine-like. The ultimate goal of speech synthesis systems is to pass a Turing test of hearing. Clearly, the state of the art in text-to-speech has much to improve. However, speech synthesis… >>> More
Verilog errors during synthesis

as seen on Stack Overflow - Search for 'Stack Overflow'
Here is the code in question: http://pastebin.com/smqUNpdt When I do a syntax check, everything is okay. But when I try to synthesize with XST I get the following errors: ERROR:Xst:870 - "fibonacci.v" line 42: Can not simplify operator DIV. ERROR:Xst:899 - "fibonacci.v" line 29: The logic for <out>… >>> More
Is algebraic sound synthesis possible?

as seen on Stack Overflow - Search for 'Stack Overflow'
Lets say you have an normal song with two layers, one instrumental and another of just vocals. Now lets say you also have just the instrumental layer. Is it possible to "subtract" the instrumentals and obtain the pure vocals? Is there going to be loss? How would I go about performing this specific… >>> More