Verilog Posedge Problem

Posted by Cenoc on Stack Overflow See other posts from Stack Overflow or by Cenoc
Published on 2010-05-18T01:13:35Z Indexed on 2010/05/18 1:20 UTC
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verilog

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clock

I'm having the following problem; I have a clk at 50MHz, but I want something else to run with a posedge signal whenever ready, but for some reason it always goes at the 50MHz, although I explicitly write otherwise, do you guys have any suggestions?

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