Simulators for thread scheduling on multicore
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Published on 2014-06-11T03:21:15Z
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I am seeking a simulator for thread scheduling at multi-core architecture, that is mapping threads to the cores at runtime. During runtime, simulator collects overall cache and IPC statistics. I checked below simulators, but seems there are not sufficient for me:
Simplescalar: A simulator only for single core.
SESC: multiprocessor simulator with detailed power, thermal, and performance models,
QSim: provides instruction-level control of the emulated environment and detailed information about the executing instruction stream.
It seems both SESC and QSim supports instructions scheduling instead of thread scheduling on the cores? Anyone can help provide some clues or share experience for this part?
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