Should you remove all warnings in your Verilog or VHDL design? Wh or why not?

Posted by Brian Carlton on Stack Overflow See other posts from Stack Overflow or by Brian Carlton
Published on 2010-04-27T15:01:21Z Indexed on 2010/04/27 15:03 UTC
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verilog

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vhdl

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altera

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fpga

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visual-basic

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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