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  • Toshiba Satellite C850, Wlan, rtl8188ce not working

    - by Hans
    I installed Ubunto 12.04 onto a brand new Toshiba Satellite C850 64 bit laptop. Wlan does not work, Tries to connect, gives up after some time. $Windows7 works 100%. There appears to be a problem with the driver. The actual hardware is a rtl8188ce chip. The firmware & driver loaded by Ubunto is for the rtl8192ce chip. How can I get and install a driver and firmware for Ubunto 12.04 and rtl8188ce?

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  • Acer Revo (ION platform) + Maverick + 5.1 surround over HDMI

    - by Oli
    I've had a turbulent relationship with my media centre box. Every upgrade I perform on it seems to bring a brand new set of audio issues (the opposite of my desktop where things seem to get better and better). It's a Acer Revo 3600. That's basically an low-end Intel Atom chip with a Nvidia 9400M onboard. On paper that's perfect for something like a media centre. But having just upgraded to Maverick, the sound properties box only wants to offer me stereo sound over HDMI. The exact setup goes: Revo - Onkyo AV receiver - LG TV. The Onkyo box strips off the audio (supporting 7.1 -- though we're only using 6 speakers) and feeds the video onto the TV. I'd like to get to a point where Ubuntu thinks it's doing 5.1 over HDMI, upmixing stereo to 6ch and supporting DTS/AC3 (through Boxee). I've had this working before but it's frankly been a bit of a hacktastrophe. The audio chip is recognised as Nvidia MCP79/7A HDMI in alsamixer if that helps.

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  • Cant get lm-sensors to load ATI Radeon temp and fan or output all settings

    - by woody
    New to Linux and having minor issues :/ . I followed this guide initially but did not recieve the proper output and did not show my ATI Radeon HD 5000 temp or fan speed. Then used this guide, same problems exhibited. No issues installing and no errors. I think its not reading i2c for some reason. The proprietary driver is installed and functioning correctly according fglrxinfo. I can use aticonfig commands and view both temp and fan. Any ideas on how to get the ATI Radeon sensors working under 'sensors'? When i run 'sudo sensors-detect' this is my ouput # sensors-detect revision 5984 (2011-07-10 21:22:53 +0200) # System: LENOVO IdeaPad Y560 (laptop) # Board: Lenovo KL3 This program will help you determine which kernel modules you need to load to use lm_sensors most effectively. It is generally safe and recommended to accept the default answers to all questions, unless you know what you're doing. Some south bridges, CPUs or memory controllers contain embedded sensors. Do you want to scan for them? This is totally safe. (YES/no): y Silicon Integrated Systems SIS5595... No VIA VT82C686 Integrated Sensors... No VIA VT8231 Integrated Sensors... No AMD K8 thermal sensors... No AMD Family 10h thermal sensors... No AMD Family 11h thermal sensors... No AMD Family 12h and 14h thermal sensors... No AMD Family 15h thermal sensors... No AMD Family 15h power sensors... No Intel digital thermal sensor... Success! (driver `coretemp') Intel AMB FB-DIMM thermal sensor... No VIA C7 thermal sensor... No VIA Nano thermal sensor... No Some Super I/O chips contain embedded sensors. We have to write to standard I/O ports to probe them. This is usually safe. Do you want to scan for Super I/O sensors? (YES/no): y Probing for Super-I/O at 0x2e/0x2f Trying family `National Semiconductor/ITE'... Yes Found unknown chip with ID 0x8502 Probing for Super-I/O at 0x4e/0x4f Trying family `National Semiconductor/ITE'... No Trying family `SMSC'... No Trying family `VIA/Winbond/Nuvoton/Fintek'... No Trying family `ITE'... No Some hardware monitoring chips are accessible through the ISA I/O ports. We have to write to arbitrary I/O ports to probe them. This is usually safe though. Yes, you do have ISA I/O ports even if you do not have any ISA slots! Do you want to scan the ISA I/O ports? (YES/no): y Probing for `National Semiconductor LM78' at 0x290... No Probing for `National Semiconductor LM79' at 0x290... No Probing for `Winbond W83781D' at 0x290... No Probing for `Winbond W83782D' at 0x290... No Lastly, we can probe the I2C/SMBus adapters for connected hardware monitoring devices. This is the most risky part, and while it works reasonably well on most systems, it has been reported to cause trouble on some systems. Do you want to probe the I2C/SMBus adapters now? (YES/no): y Using driver `i2c-i801' for device 0000:00:1f.3: Intel 3400/5 Series (PCH) Now follows a summary of the probes I have just done. Just press ENTER to continue: Driver `coretemp': * Chip `Intel digital thermal sensor' (confidence: 9) To load everything that is needed, add this to /etc/modules: #----cut here---- # Chip drivers coretemp #----cut here---- If you have some drivers built into your kernel, the list above will contain too many modules. Skip the appropriate ones! Do you want to add these lines automatically to /etc/modules? (yes/NO) My output for 'sensors' is: acpitz-virtual-0 Adapter: Virtual device temp1: +58.0°C (crit = +100.0°C) coretemp-isa-0000 Adapter: ISA adapter Core 0: +56.0°C (high = +84.0°C, crit = +100.0°C) Core 1: +57.0°C (high = +84.0°C, crit = +100.0°C) Core 2: +58.0°C (high = +84.0°C, crit = +100.0°C) Core 3: +57.0°C (high = +84.0°C, crit = +100.0°C) and my '/etc/modules' is: # /etc/modules: kernel modules to load at boot time. # # This file contains the names of kernel modules that should be loaded # at boot time, one per line. Lines beginning with "#" are ignored. lp rtc # Generated by sensors-detect on Fri Nov 30 23:24:31 2012 # Chip drivers coretemp

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  • Organization &amp; Architecture UNISA Studies &ndash; Chap 5

    - by MarkPearl
    Learning Outcomes Describe the operation of a memory cell Explain the difference between DRAM and SRAM Discuss the different types of ROM Explain the concepts of a hard failure and a soft error respectively Describe SDRAM organization Semiconductor Main Memory The two traditional forms of RAM used in computers are DRAM and SRAM DRAM (Dynamic RAM) Divided into two technologies… Dynamic Static Dynamic RAM is made with cells that store data as charge on capacitors. The presence or absence of charge in a capacitor is interpreted as a binary 1 or 0. Because capacitors have natural tendency to discharge, dynamic RAM requires periodic charge refreshing to maintain data storage. The term dynamic refers to the tendency of the stored charge to leak away, even with power continuously applied. Although the DRAM cell is used to store a single bit (0 or 1), it is essentially an analogue device. The capacitor can store any charge value within a range, a threshold value determines whether the charge is interpreted as a 1 or 0. SRAM (Static RAM) SRAM is a digital device that uses the same logic elements used in the processor. In SRAM, binary values are stored using traditional flip flop logic configurations. SRAM will hold its data as along as power is supplied to it. Unlike DRAM, no refresh is required to retain data. SRAM vs. DRAM DRAM is simpler and smaller than SRAM. Thus it is more dense and less expensive than SRAM. The cost of the refreshing circuitry for DRAM needs to be considered, but if the machine requires a large amount of memory, DRAM turns out to be cheaper than SRAM. SRAMS are somewhat faster than DRAM, thus SRAM is generally used for cache memory and DRAM is used for main memory. Types of ROM Read Only Memory (ROM) contains a permanent pattern of data that cannot be changed. ROM is non volatile meaning no power source is required to maintain the bit values in memory. While it is possible to read a ROM, it is not possible to write new data into it. An important application of ROM is microprogramming, other applications include library subroutines for frequently wanted functions, System programs, Function tables. A ROM is created like any other integrated circuit chip, with the data actually wired into the chip as part of the fabrication process. To reduce costs of fabrication, we have PROMS. PROMS are… Written only once Non-volatile Written after fabrication Another variation of ROM is the read-mostly memory, which is useful for applications in which read operations are far more frequent than write operations, but for which non volatile storage is required. There are three common forms of read-mostly memory, namely… EPROM EEPROM Flash memory Error Correction Semiconductor memory is subject to errors, which can be classed into two categories… Hard failure – Permanent physical defect so that the memory cell or cells cannot reliably store data Soft failure – Random error that alters the contents of one or more memory cells without damaging the memory (common cause includes power supply issues, etc.) Most modern main memory systems include logic for both detecting and correcting errors. Error detection works as follows… When data is to be read into memory, a calculation is performed on the data to produce a code Both the code and the data are stored When the previously stored word is read out, the code is used to detect and possibly correct errors The error checking provides one of 3 possible results… No errors are detected – the fetched data bits are sent out An error is detected, and it is possible to correct the error. The data bits plus error correction bits are fed into a corrector, which produces a corrected set of bits to be sent out An error is detected, but it is not possible to correct it. This condition is reported Hamming Code See wiki for detailed explanation. We will probably need to know how to do a hemming code – refer to the textbook (pg. 188 – 189) Advanced DRAM organization One of the most critical system bottlenecks when using high-performance processors is the interface to main memory. This interface is the most important pathway in the entire computer system. The basic building block of main memory remains the DRAM chip. In recent years a number of enhancements to the basic DRAM architecture have been explored, and some of these are now on the market including… SDRAM (Synchronous DRAM) DDR-DRAM RDRAM SDRAM (Synchronous DRAM) SDRAM exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. SDRAM employs a burst mode to eliminate the address setup time and row and column line precharge time after the first access In burst mode a series of data bits can be clocked out rapidly after the first bit has been accessed SDRAM has a multiple bank internal architecture that improves opportunities for on chip parallelism SDRAM performs best when it is transferring large blocks of data serially There is now an enhanced version of SDRAM known as double data rate SDRAM or DDR-SDRAM that overcomes the once-per-cycle limitation of SDRAM

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  • For business information and web traffic T4 and Solaris 11 stand head and shoulders above the crowd

    - by rituchhibber
    Everyone is talking about encryption of business information and web traffic. T4 and Solaris 11 stand head and shoulders above the crowd. Each T4 chip has 8 crypto accelerators inside the chip - that means there are 32 in a T4-4.  These are faster and offer more algorithms than almost all standalone devices and it is all free with T4!  What are you waiting for?Please contact Lucy Hillman or Graham Scattergood for more details.Your weekly tea time soundbite of the latest UK news, updates and initiatives on the SPARC T Series servers. T4 good news, best practice and feedback is always welcome.

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  • HW resources for the device driver [closed]

    - by VladimirLenin
    Need to provide memory and IRQ resources to the Linux kernel in order to bring up the CAN controller. Have no idea how to get them. Below is the structure I need to fill in. This structure I have taken for example, this is for the Run-Time Clock, but I need for CAN controller. Both are on the same board, and there are constants for RT Clock (and all other devices), but not for my CAN chip. When looking at the subject chip driver's code (sp_probe() function), I see it needs the same type resources. struct resource tegra_rtc_resources[] = { [0] = { .start = ???, .end = ???, .flags = IORESOURCE_MEM, }, [1] = { .start = ???, .end = ???, .flags = IORESOURCE_IRQ, }, };

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  • Linux will not activate wireless after device has been re-enabled

    - by XHR
    Using a Eee 900A netbook by Asus. By pressing Fn + F2, I can disable or enable the wireless chip on the netbook, a blue LED indicates the status. I've been able to connect to wireless networks just fine with this netbook. However, if the wireless chip ever becomes disabled, I have to reboot to get my network connection back. This generally happens when suspending. For some reason the LED will be off and I have to hit Fn + F2 for it to light up again. However, after doing so, Linux will not reconnect to the network. It simply changes the wireless status from "wireless is disabled" to "device not ready". Even worse, I've recently had issues with the chip being enabled at boot, thus making it nearly impossible to get connected. I've searched around on-line but haven't found much of anything useful on this. This happens on all kinds of different distros including Ubuntu 9.10 Netbook, EeeBuntu 4 beta, Jolicloud and Ubuntu 10.04 Netbook. Edit I noticed this question is getting a lot of views. To give a quick update, I never did resolve this issue with the given distro's. However, I'm currently running Ubuntu 10.10 netbook edition and this issue has gone away.

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  • what does process geometry mean?

    - by wenlujon
    from ARM DDI 01001, there is a term: process geometry, does it mean the chip size? Caches and write buffers to improve average system performance are now commonplace in ARM® memory systems. Core clock rates have increased at a faster rate than memory access times over recent years. This factor, and smaller process geometries, the economics of on-chip memory, and system power constraints have encouraged the use of caches to meet growing system demands. thanks.

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  • Innovative SPARC: Lighting a Fire Under Oracle's New Hardware Business

    - by Paulo Folgado
    "There's a certain level of things you can do with commercially available parts," says Oracle Executive Vice President Mike Splain. But, he notes, you can do so much more if you design the parts yourself. Mike Splain,EVP, OracleYou can, for example, design cryptographic accelerators into your microprocessors so customers can run their networks fully encrypted if they choose.Of course, it helps if you've already built multiple processing "cores" into those chips so they can handle all that encrypting and decrypting while still getting their other work done.System on a ChipAs the leader of Oracle Microelectronics, Mike knows how implementing clever innovations in silicon can give systems a real competitive advantage.The SPARC microprocessors that his team designed at Sun pioneered the concept of multiple cores several years ago, and the UltraSPARC T2 processor--the industry's first "system on a chip"--packs up to eight cores per chip, each running as many as eight threads at once. That's the most cores and threads of any general-purpose processor. Looking back, Mike points out that the real value of large enterprise-class servers was their ability to run a lot of very large applications in parallel."The beauty of our CMT [chip multi-threading] machines is you can get that same kind of parallel-processing capability at a much lower cost and in a much smaller footprint," he says.The Whole StackWhat has Mike excited these days is that suddenly the opportunity to innovate is much bigger as part of Oracle."In my group, we used to look up the software stack and say, 'We can do any innovation we want, provided the only thing we have to change is what's in the Solaris operating system'--or maybe Java," he says. "If we wanted to change things beyond that, we'd have to go outside the walls of Sun and we'd have to convince the vendors: 'You have to align with us, you have to test with us, you have to build for us, and then you'll reap the benefits.' Now we get access to the entire stack. We can look all the way through the stack and say, 'Okay, what would make the database go faster? What would make the middleware go faster?'"Changing the WorldMike and his microelectronics team also like the fact that Oracle is not just any software company. We're #1 in database, middleware, business intelligence, and more."We're like all the other engineers from Sun; we believe we can change the world, if we can just figure out how to get people to pay attention to us," he says. "Now there's a mechanism at Oracle--much more so than we ever had at Sun."He notes, too, that every innovation in SPARC has involved some combination of hardware and softwareoptimization."Take our cryptography framework, for example. Sure, we can accelerate rapidly, but the Solaris OS has to provide the right set of interfaces that applications can tap into," Mike says. "Same thing with our multicore architecture. We have to have software that can utilize all those threads and run in parallel." His engineers, he points out, have never been interested in producing chips that sell as mere components."Our chips are always designed to go into systems and be combined with various pieces of software," he says. "Our job is to enable the creation of systems."

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  • Why Haven’t NFC Payments Taken Off?

    - by David Dorf
    With the EMV 2015 milestone approaching rapidly, there’s been renewed interest in smartcards, those credit cards with an embedded computer chip.  Back in 1996 I was working for a vendor helping Visa introduce a stored-value smartcard to the US.  Visa Cash was debuted at the 1996 Olympics in Atlanta, and I firmly believed it was the beginning of a cashless society.  (I later worked on MasterCard’s system called Mondex, from the UK, which debuted the following year in Manhattan). But since you don’t have a Visa Cash card in your wallet, it’s obvious the project never took off.  It was convenient for consumers, faster for merchants, and more cost-effective for banks, so why did it fail?  All emerging payment systems suffer from the chicken-and-egg dilemma.  Consumers won’t carry the cards if few merchants accept them, and merchants won’t install the terminals if few consumers have cards. Today’s emerging payment providers are in a similar pickle.  There has to be enough value for all three constituents – consumers, merchants, banks – to change the status quo.  And it’s not enough to exceed the value, it’s got to be a leap in value, because people generally resist change.  ATMs and transit cards are great examples of this, and airline kiosks and self-checkout systems are to a lesser extent. Although Google Wallet and ISIS, the two leading NFC payment platforms in the US, have shown strong commitment, there’s been very little traction.  Yes, I can load my credit card number into my phone then tap to pay, but what was the incremental value over swiping my old card?  For it to be a leap in value, it has to offer more than just payment, which I can do very easily today.  The other two ingredients are thought to be loyalty programs and digital coupons, but neither Google nor ISIS really did them well. Of course a large portion of the mobile phone market doesn’t even support NFC thanks to Apple, and since it’s not in their best interest that situation is unlikely to change.  Another issue is getting access to the “secure element,” the chip inside the phone where accounts numbers can be held securely.  Telco providers and handset manufacturers own that area, and they’re not willing to share with banks.  (Host Card Emulation, which has been endorsed by MasterCard and Visa, might be a solution.) Square recently gave up on its wallet, and MCX (the group of retailers trying to create a mobile payment platform) is very slow out of the gate.  That leaves PayPal and a slew of smaller companies trying to introduce easier ways to pay. But is it really so cumbersome to carry and swipe (soon to insert) a credit card?  Aren’t there more important problems to solve in the retail customer experience?  Maybe Apple will come up with some novel way to use iBeacons and fingerprint identification to make payments, but for now I think we need to focus on upgrading to Chip-and-PIN and tightening security.  In the meantime, NFC payments will continue to struggle.

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  • Custom sectionGroup and Section App.config

    - by fampinheiro
    <configSections> <section name="castle" type="Castle.Windsor.Configuration.AppDomain.CastleSectionhandler, Castle.Windsor" /> <sectionGroup name="codegarten"> <section name="configuration" type="Tmp.StartupCodegartenConfigSection, Tmp" /> <section name="apache" type="Tmp.StartupApacheConfigSection, Tmp" /> </sectionGroup> </configSections> When i use msdn main to see all the sections i get this error, Unhandled Exception: System.Configuration.ConfigurationErrorsException: An error occurred creating the configuration section handler for codegarten/apache: Coul d not load type 'Tmp.StartupApacheConfigSection' from assembly 'Tmp'. (D:\Codega rten\trunk\Codegarten\Tmp\bin\Debug\Tmp.exe.Config line 8) ---> System.TypeLoadE xception: Could not load type 'Tmp.StartupApacheConfigSection' from assembly 'Tm p'. at System.Configuration.TypeUtil.GetTypeWithReflectionPermission(IInternalCon figHost host, String typeString, Boolean throwOnError) at System.Configuration.MgmtConfigurationRecord.CreateSectionFactory(FactoryR ecord factoryRecord) at System.Configuration.BaseConfigurationRecord.FindAndEnsureFactoryRecord(St ring configKey, Boolean& isRootDeclaredHere) --- End of inner exception stack trace --- at System.Configuration.BaseConfigurationRecord.FindAndEnsureFactoryRecord(St ring configKey, Boolean& isRootDeclaredHere) at System.Configuration.BaseConfigurationRecord.GetSectionRecursive(String co nfigKey, Boolean getLkg, Boolean checkPermission, Boolean getRuntimeObject, Bool ean requestIsHere, Object& result, Object& resultRuntimeObject) at System.Configuration.ConfigurationSectionCollection.Get(String name) at System.Configuration.ConfigurationSectionCollection.<GetEnumerator>d__0.Mo veNext() at Tmp.Program.ShowSectionGroupInfo(ConfigurationSectionGroup sectionGroup) i n D:\Codegarten\trunk\Codegarten\Tmp\Program.cs:line 53 at Tmp.Program.ShowSectionGroupCollectionInfo(ConfigurationSectionGroupCollec tion sectionGroups) in D:\Codegarten\trunk\Codegarten\Tmp\Program.cs:line 30 at Tmp.Program.Main(String[] args) in D:\Codegarten\trunk\Codegarten\Tmp\Prog ram.cs:line 22 Thanks

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  • Figuring out the Nyquist performance limitation of an ADC on an example PIC microcontroller

    - by AKE
    I'm spec-ing the suitability of a dsPIC microcontroller for an analog-to-digital application. This would be preferable to using dedicated A/D chips and a separate dedicated DSP chip. To do that, I've had to run through some computations, pulling the relevant parameters from the datasheets. I'm not sure I've got it right -- would appreciate a check! (EDITED NOTE: The PIC10F220 in the example below was selected ONLY to walk through a simple example to check that I'm interpreting Tacq, Fosc, TAD, and divisor correctly in working through this sort of Nyquist analysis. The actual chips I'm considering for the design are the dsPIC33FJ128MC804 (with 16b A/D) or dsPIC30F3014 (with 12b A/D).) A simple example: PIC10F220 is the simplest possible PIC with an ADC Runs at clock speed of 8MHz. Has an instruction cycle of 0.5us (4 clock steps per instruction) So: Taking Tacq = 6.06 us (acquisition time for ADC, assume chip temp. = 50*C) [datasheet p34] Taking Fosc = 8MHz (? clock speed) Taking divisor = 4 (4 clock steps per CPU instruction) This gives TAD = 0.5us (TAD = 1/(Fosc/divisor) ) Conversion time is 13*TAD [datasheet p31] This gives conversion time 6.5us ADC duration is then 12.56 us [? Tacq + 13*TAD] Assuming at least 2 instructions for load/store: This is another 1 us [0.5 us per instruction] Which would give max sampling rate of 73.7 ksps (1/13.56) Supposing 8 more instructions for real-time processing: This is another 4 us Thus, total ADC/handling time = 17.56us (12.56us + 1us + 4us) So expected upper sampling rate is 56.9 ksps. Nyquist frequency for this sampling rate is therefore 28 kHz. If this is right, it suggests the (theoretical) performance suitability of this chip's A/D is for signals that are bandlimited to 28 kHz. Is this a correct interpretation of the information given in the data sheet in obtaining the Nyquist performance limit? Any opinions on the noise susceptibility of ADCs in PIC / dsPIC chips would be much appreciated! AKE

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  • Append json data to html class name

    - by user2898514
    I have a problem with my json code. I want to append each json value comes from a key to be appended to an html class name which matches the key of json data. here's my Live demo if you see the result in the life demo. it's only appending the last record. is it possible to make it show all records in order? json var json = '[{"castle":"big","commercial":"large","common":"sergio","cultural":"2009"},' + '{"castle":"big2","commercial":"large2","common":"sergio2","cultural":"20092"}]'; html <div class="castle"></div> <div class="commercial"></div> <div class="common"></div> <div class="cultural"></div> javascript var data = $.parseJSON(json); $.each(data, function(l,v) { $.each(v, function(k,o) { $('.'+k).attr('id', k+o); console.log($('#'+k+o).attr('id')); $('#'+k+o).text(o); }); }); for more illustration... I want the result in the live demo to look like this big large sergio 2009, big2 large2 sergio2 20092

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  • Windows 7 Service Pack 1 Install Failing

    - by Cu Jimmy
    I am having real trouble updating one of my machines to Win7 Service Pack 1. Its an Asus P5K board with an X9650 Quad Core Extreme chip, which is a less common type of chip. Was wondering if anyone has had issues with this kind of kit or if it may just be the motherboard is a little gone. The error message I get back from Microsoft Update is WindowsUpdate_80091007 and WindowsUpdate_dt000 which are fairly generic errors. Tried installing with the sp1 file based installer and got nowhere. The actual installer crashes with an SP Installer has crashed Its a fresh install on a fully scrubbed drive (an Intel 120GB SSD).

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  • Using 2-port LSI 2308-8e card to control 24 SAS HDDs

    - by GregC
    I would like to rely on a RAID-on-chip solution to control 24 SAS hard drives in a direct-attached environment. How would you approach this to get best bandwidth given that I'd like to spend less than $10,000 on the interconnect. I've read that LSI 2308 chip can easily handle 8-drive SSD RAID6 in hardware. I'd like to harness its power to control 24 SAS hard drives over an expander in an external enclosure. Currently I use an Infortrend S24S-G2240 external enclosure. It provides its own controller and expander. I'd like to use LSI 2308 controller for RAID6 somehow instead of the mystery controller in the enclosure. P.S. I tried to create SAS-expander as a tag, but my rep on this site is low.

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  • Sound from both speakers and headphones with SoundMAX ADI AD1986A on Windows 7: possible?

    - by oKtosiTe
    My ASUS A8N-VM CSM motherboard has an on-board sound chip–the SoundMAX ADI AD1986A. Although sound does work reliably on Windows 7, I was a bit disappointed that neither ASUS nor the manufacturer of the sound chip offer drivers for it for Windows 7 (or Vista for that matter). Among other things jack detection, output to front and read jack simultaneously and surround sound are no longer available using Microsoft's default HD Audio driver under Windows 7. Under Windows XP and several Linux distributions (Arch, Gentoo and Ubuntu) that I've tried everything works as it should. Since I switch between headphones and speakers quite often, this annoyance begs me to ask: aside from buying a sound card, is there any way to get sound from both outputs at the same time?

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  • What is the correct term for the number of bits used by an operating system

    - by benc
    Recently, some discussions came up about 32 bit vs. 64 bit implementations of operating systems. While I was composing a message about this topic, I realized that I did not know if there was a correct term for the number of bits supported by an operating system. For example, various versions of Solaris and Linux have 32bit and 64bit releases. Is the distinction "architecture"? In my experience, that has referred to chip types (Intel vs. PPC). Is it a "release"? Typically, I think of a release as a version number a consistent feature set, that might run on different architectures. Maybe it is just "architecture", after all, even though a chip family might have used several different bit sizes over time, the chips themselves are different when you jump from 32bit to 64bit.

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  • Intel PRO/1000 Server NIC on Windows latency. How to measure?

    - by Bobb
    Please note - this question is about latency of the card itself. Not latency of internet or anything else. Thank you for your attention on this matter. It is often said that good server NIC does make difference compared to low grade cards and on-board Ethernet chips. I understand that on-board chip will likely consume CPU time and stand-alone card would use its own chip. Also server card would be faster than low-grade card. Are these 2 facts explaining most of the server cards advantages over on-board and low-grade cards ethernet? How would you measure latency on the card itself? I saw some reports stating some microseconds figures of NIC latency but I dont see how to measure that... Any advise will be appreciated.

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  • How is it possible for SSD's drives to have such a good latency?

    - by tigrou
    First time i read some information about SSD's, i was surprised to learn they internally use NAND flash chips. This kind of memory is generally slow (low bandwidth) and have high latency while SSD's are just the opposite. But here is how it works : SSD drives increase their bandwidth by using several NAND flash chips in parallel. In other words, they do some data striping (aka RAID0) across several chips (done by the controller). What i don't understand is how SSD's drives have such a low latency, whereas they are using NAND chips? (or at least lot better than what a typical single NAND chip would do) EDIT: I think under-estimate NAND chip capabilities. USB drives, while powered by NAND's are mostly limited by USB protocol (which have a pretty high latency) and the USB controller. That explain their poor performance in some cases.

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  • Computer hanged in the middle of bios flashing process

    - by Stalker
    I have a laptop: Toshiba Satellite c660-17j, today I decided to update BIOS. I've downloaded bios updater from manufacturer's web site, and in the middle of flashing process computer hanged. I was waiting more than 30 minutes, but nothing was changed on the screen, i've tryed to PRESS MORE BUTTONS, but there were no reactions, so i've turned it off by removing battery (all other methods failed, even pressing power button for ~10 secs). After that computer can't start. I understand, that there's MESS in BIOS chip, and it's possible to re-flash it with hardware programmer, but I don't have it. I remember, that on some PCs (even on my eeepc) there was possibility to re-flash bios by inserting usb flash-disk (with .dat file on it, which contained BIOS), and power on PC, while holding some keys combination, then PC was switching to BIOS programming mode and re-flashed BIOS, after that it was possible to boot up normaly. Is there a way to recover computer without hardware programming BIOS chip? p.s. sorry for my english.

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  • TPM had to be reintialized: Does a new recovery password have to be uploaded to AD?

    - by MDMoore313
    Some way some how, a user's machine couldn't get read the bitlocker password off of the TPM chip, and I had to enter the recovery key (stored in AD) to get in. No big deal, but once in the machine, I tried to suspend bitlocker per recovery documentation, and got an error message about the TPM not being initialized. I knew the TPM was on and activated in the BIOS, but Windows still made me reinitialize the TPM chip, and in the process it created a new TPM owner password. I found that odd because it prompted me to save this password or print it (there wasn't an option not to), but it made no reference of a recovery password, nor did it back this password up to AD. After the user took her laptop and left I started thinking that if the TPM password change, does the recovery password change also? If so, that new recovery password will need to be uploaded to AD, but MS' documentation doesn't make that clear, and doesn't back up the new recovery key (if one exists) to AD automatically when the group policy says it must, and from a network standpoint AD is accessible.

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  • Silverlight Cream for April 19, 2010 -- #841

    - by Dave Campbell
    In this Issue: Michael Washington, Jeremy Likness, Giorgetti Alessandro, Antoni Dol, Mike Taulty, and Braulio Diez. Shoutout: Bart Czernicki lists compelling reasons to use Silverlight 4 for LOB apps: Silverlight 4 - What is New for Business Intelligence Scenarios From SilverlightCream.com: Silverlight Advanced MVVM Video Player After the initial posting on his Simple MVVM Video player, Michael Washington got some feedback and decided to do a part 2 demonstrating exactly how easy it is to customize... great tutorial and all the code. Model-View-ViewModel (MVVM) Explained Jeremy Likness has a post up that begins "The purpose of this post is to provide an introduction to the Model-View-ViewModel (MVVM) pattern." -- 'nuff said... If you're not there yet, get there now :) Castle Windsor – Silverlight 4 binaries Giorgetti Alessandro has produced workable Castle Windsor binaries for Silverlight 4. No Unit Tests at this point, but read the post for that information. Silverlight Togglebutton Push Pin Style with IsoStore Antoni Dol has a very nice ToggleButton redone as a pushpin for pinning an app, plus it saves the pinned information to Isolated Storage ... all with source! Silverlight and Xml Binding Mike Taulty fleshes out a sketchy idea he has surrounding databinding Silverlight to XML data by using the ability to databind to string indexers and XPath support. WinToolbar Silverlight widget available on Codeplex Braulio Diez announced a Toolbar library that he and Sebastian Stehlehave posted on CodePlex that looks awesome... you may as well just go get it now, you're going to want to! Stay in the 'Light! Twitter SilverlightNews | Twitter WynApse | WynApse.com | Tagged Posts | SilverlightCream Join me @ SilverlightCream | Phoenix Silverlight User Group Technorati Tags: Silverlight    Silverlight 3    Silverlight 4    Windows Phone MIX10

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