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• Makefile error: Unexpected end of line seen

  - by Winston C. Yang

  Trying to install Git, I ran configure and make, but got the following error message: make: Fatal error in reader: Makefile, line 221: Unexpected end of line seen The Makefile looks like: 218: GIT-VERSION-FILE: FORCE 219: @$(SHELL_PATH) ./GIT-VERSION-GEN 220: -include GIT-VERSION-FILE 221: 222: uname_S := $(shell sh -c…

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• ISO C90 forbids mixed declarations and code Warning [Kernel Module Makefile]

  - by djTeller

  Hi, I'm trying to compile a linux kernel module using a Makefile which looks like so: obj-m += main.o all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean and i'm getting the following warning: main.c:54: warning: ISO C90 forbids mixed declarations and…

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• GNU make variables in Makefile

  - by JTom

  Hi, I would like to create a Makefile which also creates a simple script for running the compiled application. I have something like the following: @touch $(SCRIPT) @echo LD_LIBRARY_PATH=$(LIB_DIR) $(APP_DIR)/$(APP) $1 $2 $3 $4 $5 $6 > $(SCRIPT) @chmod +x $(SCRIPT) @echo Script successfully created. And I want $1 $2 ... to appear in the…

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• Makefile issue with compiling a C++ program

  - by Steve

  I recently got MySQL compiled and working on Cygwin, and got a simple test example from online to verify that it worked. The test example compiled and ran successfully. However, when incorporating MySQL in a hobby project of mine it isn't compiling which I believe is due to how the Makefile is setup, I have no experience with Makefiles and…

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• Compiling C Source with Makefile in Windows

  - by humoeba

  I'm trying to compile a downloaded program in Windows. The program is usually run in Linux, but is programmed to also run in Windows (the code has #if defined(_WIN32)'s in it, and claims to work with borland free tools). When I try to use make from the command line, it tells me "Incorrect command line argument: -C". In the makefile,…

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• Whats wrong with my makefile

  - by user577220

  ##################################################################### # This is the filesystem makefile "make_BuddyAlloc". # Author:Michael Gomes # Date:2 jan 2011 ###################################################################### #variable defination CC = gcc CFLAGS = -g -O2 SRC_DIR=src INC_DIR=inc OBJ_DIR=obj #List of source…

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• Makefile won't copy .o to obj/ and target to bin/ folders

  - by about blank

  I'm trying to write a Makefile which will copy its target and objects to bin/ and obj/ directories, respectively. Yet, when I try to run it I get the following error: nasm -f elf64 -g -F stabs main.asm -l spacelander.lst ld -o spacelander obj/main.o ld: cannot find obj/main.o: No such file or directory make: *** [spacelander]…

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• Makefile for DOS/Windows and Cygwin

  - by Thomas Matthews

  I need to have a makefile work under DOS (Windows) and Cygwin. I having problems with the makefile detecting the OS correctly and setting appropriate variables. The objective is to set variables for the following commands, then invoke the commands in rules using the variables: Delete file: rm in Cygwin, del in DOS.…

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• Compile C++ file as objective-c++ using makefile

  - by Vikas

  I'm trying to compile .cpp files as objective-c++ using makefile as few of my cpp file have objective code. I added -x objective-c++ as complier option and started getting stray /327 in program error( and lots of similar error with different numbers after /). The errors are around 200. But when I change the encoding of…

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• Converting Makefile to Visual Studio Terminology Questions (First time using VS)

  - by Ukko

  I am an old Unix guy who is converting a makefile based project over to Microsoft Visual Studio, I got tasked with this because I understand the Makefile which chokes VS's automatic import tools. I am sure there is a better way than what I am doing but we are making things fit into the customer's environment and that…

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• eclipse show errors but compiles when external makefile

  - by Anthony

  I have some c++ code using CImg and Eigen libraries. At the c++ code I define a plugin like this #define cimg_plugin1 "my_plugin.h" #include "CImg.h" The plugin contains many method definitions that are used at the c++ code. I also have a makefile that when called from the command line (./make), allows me to…

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• Makefile; mirroring a growing tree through a process

  - by Martineau

  I would like to periodically mirror a growing tree, say, from $in to $out, doing a process in between (saving the only file header). As; #!/bin/bash in=./segd out=./db for f in `find $in -name "*.segd"`;do # Deduct output (dir + name) d=`dirname $f|perl -pe 's!'$in'!'$out'!'` n=`basename $f|perl…

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• makefile: execute one target from another target plus additional commands

  - by cschol

  I have a makefile with something like the following targets: install: do a whole bunch of stuff to build and install dist: install cp README.txt $(INSTALL_DIR) zip $(INSTALL_DIR) I am trying to not repeat the commands from target install and make dist execute install first before executing its…

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• Using target-specific variable in makefile

  - by James Johnston

  I have the following makefile: OUTPUTDIR = build all: v12target v13target v12target: INTDIR = v12 v12target: DoV12.avrcommontargets v13target: INTDIR = v13 v13target: DoV13.avrcommontargets %.avrcommontargets: $(OUTPUTDIR)/%.elf @true $(OUTPUTDIR)/%.elf: $(OUTPUTDIR)/$(INTDIR)/main.o @echo TODO…

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• Makefile: finding include/lib for libraries installed through macports

  - by Henk

  Libraries/include files installed by macports go in /opt/local/lib and /opt/local/include, neither of which are scanned by gcc/ld by default. As a result, a project I'm working on won't compile in that environment. Should this be fixed by manually adding -L/opt/local/lib to my Makefile's LDFLAGS (and…

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• How to fix this Makefile

  - by Phenom

  I want my Makefile to be as simple as possible and still function. This is what it looks like. load: load.cpp g++ load.cpp -g -o load list: list.cpp g++ list.cpp -g -o list It worked fine when there was only one entry. But when I added the second entry, it doesn't check to see if it's…

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• Is it possible to create a multi-line string variable in a Makefile

  - by jonathon-jongsma

  I want to create a makefile variable that is a multi-line string (e.g. the body of an email release announcement). something like ANNOUNCE_BODY=" Version $(VERSION) of $(PACKAGE_NAME) has been released It can be downloaded from $(DOWNLOAD_URL) etc, etc" But I can't seem to find a way to do…

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• Run script before compilation in Makefile

  - by Werner

  Hi, in a Makefile, I have: all: $(PROG) $(PROG): $(CPP_OBJS) $(CPP_LD) $(CPP_LD_FLAGS) $(CPP_OBJS) -o $(PROG) I would like to add some script before the compilation so I tried: all: $(PROG) $(PROG): $(CPP_OBJS) sh script.sh ; $(CPP_LD) $(CPP_LD_FLAGS) $(CPP_OBJS) -o…

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• makefile extension

  - by Happy Mittal

  I wanted to create a makefile. So I wrote instructions in a notepad file. But what extension should I give while saving this file?

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• choosing which main() to use in the Makefile

  - by Jules Olléon

  In a C project, I have a main() function in several files. When I compile I thus have an error "multiple declarations of main". Is it possible to choose in the Makefile which one of those main() functions should be used to compile ? (the other ones would then be ignored...)

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• Help in understanding EXPORTS in Makefile.in

  - by michael

  Hi, In the Makefile.in of an existing project, it has this: EXPORTS = \ gtkmozembed.h \ gtkmozembed_glue.cpp \ gtkmozembed_internal.h Can you please tell me what does EXPORTS mean? Thank you.

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• makefile problem

  - by mistique

  Hello I have a problem while trying to run a makefile. I change the path where my java install folder is(C:\Program Files\Java\jdk1.6.0_18\bin), but when I try to run 'make' from my command line I receive : 'make' is not recognized as an internal or external command, operable program or…

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• How to create a file using Makefile

  - by user306988

  Hi, I want to create a .c file from a Makefile. Content of that C file is as follows: char *variable1 = $(VAR1_FROM_MAKEFILE); char *variable2 = $(VAR2_FROM_MAKEFILE); Is it possible? Thanks in advance

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• makefile pattern rules: single wildcard, multiple instances in prerequisite

  - by johndashen

  Hi all, hopefully this is a basic question about make pattern rules: I want to use a wildcard more than once in a prerequisite for a rule, i.e. in my Makefile I have data/%P1.m: $(PROJHOME)/data/%/ISCAN/%P1.RAW @echo " Writing temporary matlab file for $*" # do…

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• Creating a project, from Makefile to static/dynamic libraries in UNIX

  - by Sasha

  Guys, would you describe a few things about c++ building blocks, on unix. I want to create an application that links against static libs and dynamic libs (.so). Question 1: How do I create static library using gcc/g++ ?How do I make my app link against it. Question 2: How…

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